SLUSD04B July   2018  – February 2019 BQ25150

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Solution Area
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Linear Charger and Power Path
        1. 8.3.1.1 Battery Charging Process
          1. 8.3.1.1.1 Pre-Charge
          2. 8.3.1.1.2 Fast Charge
          3. 8.3.1.1.3 Pre-Charge to fast Charge Transitions and Charge Current Ramping
          4. 8.3.1.1.4 Termination
        2. 8.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 8.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM)
        4. 8.3.1.4 Dynamic Power Path Management Mode (DPPM)
        5. 8.3.1.5 Battery Supplement Mode
      2. 8.3.2  Protection Mechanisms
        1. 8.3.2.1 Input Over-Voltage Protection
        2. 8.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 8.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 8.3.2.4 Battery Short and Over Current Protection
        5. 8.3.2.5 PMID Short Circuit
        6. 8.3.2.6 Maximum Allowable Charging Current (IMAX)
      3. 8.3.3  ADC
        1. 8.3.3.1 ADC Operation in Active Battery Mode and Low Power Mode
        2. 8.3.3.2 ADC Operation When VIN Present
        3. 8.3.3.3 ADC Measurements
        4. 8.3.3.4 ADC Programmable Comparators
      4. 8.3.4  VDD LDO
      5. 8.3.5  Load Switch / LDO Output and Control
      6. 8.3.6  PMID Power Control
      7. 8.3.7  MR Wake and Reset Input
        1. 8.3.7.1 MR Wake or Short Button Press Functions
        2. 8.3.7.2 MR Reset or Long Button Press Functions
      8. 8.3.8  14-second Watchdog for HW Reset
      9. 8.3.9  Faults Conditions and Interrupts (INT)
        1. 8.3.9.1 Flags and Fault Condition Response
      10. 8.3.10 Power Good (PG) Pin
      11. 8.3.11 External NTC Monitoring (TS)
        1. 8.3.11.1 TS Thresholds
      12. 8.3.12 External NTC Monitoring (ADCIN)
      13. 8.3.13 I2C Interface
        1. 8.3.13.1 F/S Mode Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 Ship Mode
      2. 8.4.2 Low Power
      3. 8.4.3 Active Battery
      4. 8.4.4 Charger/Adapter Mode
      5. 8.4.5 Power-Up/Down Sequencing
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
        1. 8.5.1.1  STAT0 Register (Address = 0x0) [reset = X]
          1. Table 10. STAT0 Register Field Descriptions
        2. 8.5.1.2  STAT1 Register (Address = 0x1) [reset = X]
          1. Table 11. STAT1 Register Field Descriptions
        3. 8.5.1.3  STAT2 Register (Address = 0x2) [reset = X]
          1. Table 12. STAT2 Register Field Descriptions
        4. 8.5.1.4  FLAG0 Register (Address = 0x3) [reset = 0x0]
          1. Table 13. FLAG0 Register Field Descriptions
        5. 8.5.1.5  FLAG1 Register (Address = 0x4) [reset = 0x0]
          1. Table 14. FLAG1 Register Field Descriptions
        6. 8.5.1.6  FLAG2 Register (Address = 0x5) [reset = 0x0]
          1. Table 15. FLAG2 Register Field Descriptions
        7. 8.5.1.7  FLAG3 Register (Address = 0x6) [reset = 0x0]
          1. Table 16. FLAG3 Register Field Descriptions
        8. 8.5.1.8  MASK0 Register (Address = 0x7) [reset = 0x0]
          1. Table 17. MASK0 Register Field Descriptions
        9. 8.5.1.9  MASK1 Register (Address = 0x8) [reset = 0x0]
          1. Table 18. MASK1 Register Field Descriptions
        10. 8.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]
          1. Table 19. MASK2 Register Field Descriptions
        11. 8.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
          1. Table 20. MASK3 Register Field Descriptions
        12. 8.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]
          1. Table 21. VBAT_CTRL Register Field Descriptions
        13. 8.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]
          1. Table 22. ICHG_CTRL Register Field Descriptions
        14. 8.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]
          1. Table 23. PCHRGCTRL Register Field Descriptions
        15. 8.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]
          1. Table 24. TERMCTRL Register Field Descriptions
        16. 8.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]
          1. Table 25. BUVLO Register Field Descriptions
        17. 8.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]
          1. Table 26. CHARGERCTRL0 Register Field Descriptions
        18. 8.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0x42]
          1. Table 27. CHARGERCTRL1 Register Field Descriptions
        19. 8.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x1]
          1. Table 28. ILIMCTRL Register Field Descriptions
        20. 8.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]
          1. Table 29. LDOCTRL Register Field Descriptions
        21. 8.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]
          1. Table 30. MRCTRL Register Field Descriptions
        22. 8.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]
          1. Table 31. ICCTRL0 Register Field Descriptions
        23. 8.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
          1. Table 32. ICCTRL1 Register Field Descriptions
        24. 8.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x0]
          1. Table 33. ICCTRL2 Register Field Descriptions
        25. 8.5.1.25 ADCCTRL0 Register (Address = 0x40) [reset = 0x2]
          1. Table 34. ADCCTRL0 Register Field Descriptions
        26. 8.5.1.26 ADCCTRL1 Register (Address = 0x41) [reset = 0x40]
          1. Table 35. ADCCTRL1 Register Field Descriptions
        27. 8.5.1.27 ADC_DATA_VBAT_M Register (Address = 0x42) [reset = X]
          1. Table 36. ADC_DATA_VBAT_M Register Field Descriptions
        28. 8.5.1.28 ADC_DATA_VBAT_L Register (Address = 0x43) [reset = X]
          1. Table 37. ADC_DATA_VBAT_L Register Field Descriptions
        29. 8.5.1.29 ADC_DATA_TS_M Register (Address = 0x44) [reset = X]
          1. Table 38. ADC_DATA_TS_M Register Field Descriptions
        30. 8.5.1.30 ADC_DATA_TS_L Register (Address = 0x45) [reset = X]
          1. Table 39. ADC_DATA_TS_L Register Field Descriptions
        31. 8.5.1.31 ADC_DATA_ICHG_M Register (Address = 0x46) [reset = X]
          1. Table 40. ADC_DATA_ICHG_M Register Field Descriptions
        32. 8.5.1.32 ADC_DATA_ICHG_L Register (Address = 0x47) [reset = X]
          1. Table 41. ADC_DATA_ICHG_L Register Field Descriptions
        33. 8.5.1.33 ADC_DATA_ADCIN_M Register (Address = 0x48) [reset = X]
          1. Table 42. ADC_DATA_ADCIN_M Register Field Descriptions
        34. 8.5.1.34 ADC_DATA_ADCIN_L Register (Address = 0x49) [reset = X]
          1. Table 43. ADC_DATA_ADCIN_L Register Field Descriptions
        35. 8.5.1.35 ADC_DATA_VIN_M Register (Address = 0x4A) [reset = X]
          1. Table 44. ADC_DATA_VIN_M Register Field Descriptions
        36. 8.5.1.36 ADC_DATA_VIN_L Register (Address = 0x4B) [reset = X]
          1. Table 45. ADC_DATA_VIN_L Register Field Descriptions
        37. 8.5.1.37 ADC_DATA_PMID_M Register (Address = 0x4C) [reset = X]
          1. Table 46. ADC_DATA_PMID_M Register Field Descriptions
        38. 8.5.1.38 ADC_DATA_PMID_L Register (Address = 0x4D) [reset = X]
          1. Table 47. ADC_DATA_PMID_L Register Field Descriptions
        39. 8.5.1.39 ADC_DATA_IIN_M Register (Address = 0x4E) [reset = X]
          1. Table 48. ADC_DATA_IIN_M Register Field Descriptions
        40. 8.5.1.40 ADC_DATA_IIN_L Register (Address = 0x4F) [reset = X]
          1. Table 49. ADC_DATA_IIN_L Register Field Descriptions
        41. 8.5.1.41 ADCALARM_COMP1_M Register (Address = 0x52) [reset = 0x23]
          1. Table 50. ADCALARM_COMP1_M Register Field Descriptions
        42. 8.5.1.42 ADCALARM_COMP1_L Register (Address = 0x53) [reset = 0x20]
          1. Table 51. ADCALARM_COMP1_L Register Field Descriptions
        43. 8.5.1.43 ADCALARM_COMP2_M Register (Address = 0x54) [reset = 0x38]
          1. Table 52. ADCALARM_COMP2_M Register Field Descriptions
        44. 8.5.1.44 ADCALARM_COMP2_L Register (Address = 0x55) [reset = 0x90]
          1. Table 53. ADCALARM_COMP2_L Register Field Descriptions
        45. 8.5.1.45 ADCALARM_COMP3_M Register (Address = 0x56) [reset = 0x0]
          1. Table 54. ADCALARM_COMP3_M Register Field Descriptions
        46. 8.5.1.46 ADCALARM_COMP3_L Register (Address = 0x57) [reset = 0x0]
          1. Table 55. ADCALARM_COMP3_L Register Field Descriptions
        47. 8.5.1.47 ADC_READ_EN Register (Address = 0x58) [reset = 0x0]
          1. Table 56. ADC_READ_EN Register Field Descriptions
        48. 8.5.1.48 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
          1. Table 57. TS_FASTCHGCTRL Register Field Descriptions
        49. 8.5.1.49 TS_COLD Register (Address = 0x62) [reset = 0x7C]
          1. Table 58. TS_COLD Register Field Descriptions
        50. 8.5.1.50 TS_COOL Register (Address = 0x63) [reset = 0x6D]
          1. Table 59. TS_COOL Register Field Descriptions
        51. 8.5.1.51 TS_WARM Register (Address = 0x64) [reset = 0x38]
          1. Table 60. TS_WARM Register Field Descriptions
        52. 8.5.1.52 TS_HOT Register (Address = 0x65) [reset = 0x27]
          1. Table 61. TS_HOT Register Field Descriptions
        53. 8.5.1.53 DEVICE_ID Register (Address = 0x6F) [reset = 0x20]
          1. Table 62. DEVICE_ID Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input (IN/PMID) Capacitors
        2. 9.2.2.2 VDD, LDO Input and Output Capacitors
        3. 9.2.2.3 TS
        4. 9.2.2.4 IMAX Selection
        5. 9.2.2.5 Recommended Passive Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 21. All I2C-compatible devices should recognize a start condition.

BQ25150 start_stop_lusba2.gifFigure 21. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 22). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 23) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

BQ25150 serial_inf_lusba2.gifFigure 22. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 21). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section wil result in FFh being read out.

BQ25150 i2c_bus_lusba2.gifFigure 23. Acknowledge on the I2C Bus
BQ25150 bus_proto_lusba2.gifFigure 24. Bus Protocol