SLUSD04B July   2018  – February 2019 BQ25150

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Solution Area
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Linear Charger and Power Path
        1. 8.3.1.1 Battery Charging Process
          1. 8.3.1.1.1 Pre-Charge
          2. 8.3.1.1.2 Fast Charge
          3. 8.3.1.1.3 Pre-Charge to fast Charge Transitions and Charge Current Ramping
          4. 8.3.1.1.4 Termination
        2. 8.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 8.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM)
        4. 8.3.1.4 Dynamic Power Path Management Mode (DPPM)
        5. 8.3.1.5 Battery Supplement Mode
      2. 8.3.2  Protection Mechanisms
        1. 8.3.2.1 Input Over-Voltage Protection
        2. 8.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 8.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 8.3.2.4 Battery Short and Over Current Protection
        5. 8.3.2.5 PMID Short Circuit
        6. 8.3.2.6 Maximum Allowable Charging Current (IMAX)
      3. 8.3.3  ADC
        1. 8.3.3.1 ADC Operation in Active Battery Mode and Low Power Mode
        2. 8.3.3.2 ADC Operation When VIN Present
        3. 8.3.3.3 ADC Measurements
        4. 8.3.3.4 ADC Programmable Comparators
      4. 8.3.4  VDD LDO
      5. 8.3.5  Load Switch / LDO Output and Control
      6. 8.3.6  PMID Power Control
      7. 8.3.7  MR Wake and Reset Input
        1. 8.3.7.1 MR Wake or Short Button Press Functions
        2. 8.3.7.2 MR Reset or Long Button Press Functions
      8. 8.3.8  14-second Watchdog for HW Reset
      9. 8.3.9  Faults Conditions and Interrupts (INT)
        1. 8.3.9.1 Flags and Fault Condition Response
      10. 8.3.10 Power Good (PG) Pin
      11. 8.3.11 External NTC Monitoring (TS)
        1. 8.3.11.1 TS Thresholds
      12. 8.3.12 External NTC Monitoring (ADCIN)
      13. 8.3.13 I2C Interface
        1. 8.3.13.1 F/S Mode Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 Ship Mode
      2. 8.4.2 Low Power
      3. 8.4.3 Active Battery
      4. 8.4.4 Charger/Adapter Mode
      5. 8.4.5 Power-Up/Down Sequencing
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
        1. 8.5.1.1  STAT0 Register (Address = 0x0) [reset = X]
          1. Table 10. STAT0 Register Field Descriptions
        2. 8.5.1.2  STAT1 Register (Address = 0x1) [reset = X]
          1. Table 11. STAT1 Register Field Descriptions
        3. 8.5.1.3  STAT2 Register (Address = 0x2) [reset = X]
          1. Table 12. STAT2 Register Field Descriptions
        4. 8.5.1.4  FLAG0 Register (Address = 0x3) [reset = 0x0]
          1. Table 13. FLAG0 Register Field Descriptions
        5. 8.5.1.5  FLAG1 Register (Address = 0x4) [reset = 0x0]
          1. Table 14. FLAG1 Register Field Descriptions
        6. 8.5.1.6  FLAG2 Register (Address = 0x5) [reset = 0x0]
          1. Table 15. FLAG2 Register Field Descriptions
        7. 8.5.1.7  FLAG3 Register (Address = 0x6) [reset = 0x0]
          1. Table 16. FLAG3 Register Field Descriptions
        8. 8.5.1.8  MASK0 Register (Address = 0x7) [reset = 0x0]
          1. Table 17. MASK0 Register Field Descriptions
        9. 8.5.1.9  MASK1 Register (Address = 0x8) [reset = 0x0]
          1. Table 18. MASK1 Register Field Descriptions
        10. 8.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]
          1. Table 19. MASK2 Register Field Descriptions
        11. 8.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
          1. Table 20. MASK3 Register Field Descriptions
        12. 8.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]
          1. Table 21. VBAT_CTRL Register Field Descriptions
        13. 8.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]
          1. Table 22. ICHG_CTRL Register Field Descriptions
        14. 8.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]
          1. Table 23. PCHRGCTRL Register Field Descriptions
        15. 8.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]
          1. Table 24. TERMCTRL Register Field Descriptions
        16. 8.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]
          1. Table 25. BUVLO Register Field Descriptions
        17. 8.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]
          1. Table 26. CHARGERCTRL0 Register Field Descriptions
        18. 8.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0x42]
          1. Table 27. CHARGERCTRL1 Register Field Descriptions
        19. 8.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x1]
          1. Table 28. ILIMCTRL Register Field Descriptions
        20. 8.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]
          1. Table 29. LDOCTRL Register Field Descriptions
        21. 8.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]
          1. Table 30. MRCTRL Register Field Descriptions
        22. 8.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]
          1. Table 31. ICCTRL0 Register Field Descriptions
        23. 8.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
          1. Table 32. ICCTRL1 Register Field Descriptions
        24. 8.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x0]
          1. Table 33. ICCTRL2 Register Field Descriptions
        25. 8.5.1.25 ADCCTRL0 Register (Address = 0x40) [reset = 0x2]
          1. Table 34. ADCCTRL0 Register Field Descriptions
        26. 8.5.1.26 ADCCTRL1 Register (Address = 0x41) [reset = 0x40]
          1. Table 35. ADCCTRL1 Register Field Descriptions
        27. 8.5.1.27 ADC_DATA_VBAT_M Register (Address = 0x42) [reset = X]
          1. Table 36. ADC_DATA_VBAT_M Register Field Descriptions
        28. 8.5.1.28 ADC_DATA_VBAT_L Register (Address = 0x43) [reset = X]
          1. Table 37. ADC_DATA_VBAT_L Register Field Descriptions
        29. 8.5.1.29 ADC_DATA_TS_M Register (Address = 0x44) [reset = X]
          1. Table 38. ADC_DATA_TS_M Register Field Descriptions
        30. 8.5.1.30 ADC_DATA_TS_L Register (Address = 0x45) [reset = X]
          1. Table 39. ADC_DATA_TS_L Register Field Descriptions
        31. 8.5.1.31 ADC_DATA_ICHG_M Register (Address = 0x46) [reset = X]
          1. Table 40. ADC_DATA_ICHG_M Register Field Descriptions
        32. 8.5.1.32 ADC_DATA_ICHG_L Register (Address = 0x47) [reset = X]
          1. Table 41. ADC_DATA_ICHG_L Register Field Descriptions
        33. 8.5.1.33 ADC_DATA_ADCIN_M Register (Address = 0x48) [reset = X]
          1. Table 42. ADC_DATA_ADCIN_M Register Field Descriptions
        34. 8.5.1.34 ADC_DATA_ADCIN_L Register (Address = 0x49) [reset = X]
          1. Table 43. ADC_DATA_ADCIN_L Register Field Descriptions
        35. 8.5.1.35 ADC_DATA_VIN_M Register (Address = 0x4A) [reset = X]
          1. Table 44. ADC_DATA_VIN_M Register Field Descriptions
        36. 8.5.1.36 ADC_DATA_VIN_L Register (Address = 0x4B) [reset = X]
          1. Table 45. ADC_DATA_VIN_L Register Field Descriptions
        37. 8.5.1.37 ADC_DATA_PMID_M Register (Address = 0x4C) [reset = X]
          1. Table 46. ADC_DATA_PMID_M Register Field Descriptions
        38. 8.5.1.38 ADC_DATA_PMID_L Register (Address = 0x4D) [reset = X]
          1. Table 47. ADC_DATA_PMID_L Register Field Descriptions
        39. 8.5.1.39 ADC_DATA_IIN_M Register (Address = 0x4E) [reset = X]
          1. Table 48. ADC_DATA_IIN_M Register Field Descriptions
        40. 8.5.1.40 ADC_DATA_IIN_L Register (Address = 0x4F) [reset = X]
          1. Table 49. ADC_DATA_IIN_L Register Field Descriptions
        41. 8.5.1.41 ADCALARM_COMP1_M Register (Address = 0x52) [reset = 0x23]
          1. Table 50. ADCALARM_COMP1_M Register Field Descriptions
        42. 8.5.1.42 ADCALARM_COMP1_L Register (Address = 0x53) [reset = 0x20]
          1. Table 51. ADCALARM_COMP1_L Register Field Descriptions
        43. 8.5.1.43 ADCALARM_COMP2_M Register (Address = 0x54) [reset = 0x38]
          1. Table 52. ADCALARM_COMP2_M Register Field Descriptions
        44. 8.5.1.44 ADCALARM_COMP2_L Register (Address = 0x55) [reset = 0x90]
          1. Table 53. ADCALARM_COMP2_L Register Field Descriptions
        45. 8.5.1.45 ADCALARM_COMP3_M Register (Address = 0x56) [reset = 0x0]
          1. Table 54. ADCALARM_COMP3_M Register Field Descriptions
        46. 8.5.1.46 ADCALARM_COMP3_L Register (Address = 0x57) [reset = 0x0]
          1. Table 55. ADCALARM_COMP3_L Register Field Descriptions
        47. 8.5.1.47 ADC_READ_EN Register (Address = 0x58) [reset = 0x0]
          1. Table 56. ADC_READ_EN Register Field Descriptions
        48. 8.5.1.48 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
          1. Table 57. TS_FASTCHGCTRL Register Field Descriptions
        49. 8.5.1.49 TS_COLD Register (Address = 0x62) [reset = 0x7C]
          1. Table 58. TS_COLD Register Field Descriptions
        50. 8.5.1.50 TS_COOL Register (Address = 0x63) [reset = 0x6D]
          1. Table 59. TS_COOL Register Field Descriptions
        51. 8.5.1.51 TS_WARM Register (Address = 0x64) [reset = 0x38]
          1. Table 60. TS_WARM Register Field Descriptions
        52. 8.5.1.52 TS_HOT Register (Address = 0x65) [reset = 0x27]
          1. Table 61. TS_HOT Register Field Descriptions
        53. 8.5.1.53 DEVICE_ID Register (Address = 0x6F) [reset = 0x20]
          1. Table 62. DEVICE_ID Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input (IN/PMID) Capacitors
        2. 9.2.2.2 VDD, LDO Input and Output Capacitors
        3. 9.2.2.3 TS
        4. 9.2.2.4 IMAX Selection
        5. 9.2.2.5 Recommended Passive Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Flags and Fault Condition Response

The table below details the BQ25150 behavior when a fault conditions occurs.

Table 5. Interrupt Triggers and Fault Condition Response

FAULT / FLAG DESCRIPTION INTERRUPT TRIGGER BASED ON STATUS BIT CHANGE CHARGER BEHAVIOR CHARGER SAFETY TIMER LS/LDO BEHAVIOR PMID BEHAVIOR NOTES
CHRG_CV_FLAG Set when charger enters Constant Voltage operation Rising Edge Enabled No effect N/A IN powered if VIN is valid
CHARGE_DONE_FLAG Set when charger reaches termination Rising Edge Paused- Charging resumes with VIN or CE toggle or when VRCH is reached Reset N/A IN powered if VIN is valid
IINLIM_ACTIVE_FLAG Set when Input Current Limit loop is active Rising Edge Enabled. Reduced charge current. Doubled if option is enabled N/A IN powered VIN powered unless supplement mode condition is met.
VDPPM_ACTIVE_FLAG Set when DPPM loop is active Rising Edge Enabled. Reduced charge current. Doubled if option is enabled N/A VIN powered unless supplement mode condition is met.
VINDPM_ACTIVE_FLAG Set when VINDPM loop is active Rising Edge Enabled. Reduced charge current. Doubled if option is enabled N/A VIN powered unless supplement mode condition is met.
THERMREG_ACTIVE Set when Thermal Charge Current Foldback (Thermal Regulation) loop is active Rising Edge Enabled. Reduced charge current. Doubled if option is enabled N/A VIN powered unless supplement mode condition is met.
VIN_PGOOD_FLAG Set when VIN changes PGOOD status Rising and Falling Edge If VIN_PGOOD_STAT is low, charging is disabled. Reset N/A VIN powered (if VIN_PGOOD_STAT=1) unless PMID_MODE is not 00. Interrupt will not be sent if device powers up with VIN_PGOOD condition and VBAT < VBATUVLO
VIN_OVP_FAULT_FLAG Set when VIN > VOVP Rising Edge Charging is paused until condition disappears Reset N/A BAT powered
BAT_OCP_FAULT_FLAG Set when IBAT > IBATOCP Rising Edge Disabled (BAT only condition) N/A N/A Disconnect BAT
BAT_UVLO_FAULT_FLAG Set when VBAT < VBATUVLO Rising Edge Enabled No effect N/A IN powered of VIN is valid
TS_COLD_FLAG Set when VTS > VTS_COLD Rising Edge Charging paused until condition is cleared Paused N/A IN powered of VIN is valid
TS_COOL_FLAG Set when VTS_COLD > VTS > VTS_COOL Rising Edge Enabled. Reduced charge current. Doubled if option is enabled N/A IN powered of VIN is valid
TS_WARM_FLAG Set when VTS_HOT < VTS < VTS_WARM Rising Edge Enabled. Reduce battery regulation voltage. No effect N/A IN powered of VIN is valid
TS_HOT_FLAG Set when VTS < VHOT Rising Edge Charging paused until condition is cleared Paused N/A IN powered of VIN is valid
ADC_READY_FLAG Set when ADC conversion is completed Rising Edge N/A N/A N/A N/A
COMP1_ALARM_FLAG Set when ADC measurement meets programmed condition Rising Edge N/A N/A N/A N/A
COMP2_ALARM_FLAG Set when ADC measurement meets programmed condition Rising Edge N/A N/A N/A N/A
COMP3_ALARM_FLAG Set when ADC measurement meets programmed condition Rising Edge N/A N/A N/A N/A
IMAX_ACTIVE_FLAG Set when charge current is programmed above the IMAX setting Rising Edge Enabled N/A N/A N/A
TS_OPEN_FLAG Set when VTS > VTS_OPEN Rising Edge Charging is paused until condition disappears Paused N/A N/A
WD_FAULT_FLAG Set when I2C watchdog timer expires Rising Edge Enabled N/A N/A N/A
SAFETY_TMR_FAULT_FLAG Set when safety Timer expires. Cleared after VIN or CE toggle Rising Edge Disabled until VIN or CE toggle Reset after flag is cleared N/A IN powered of VIN is valid
LS_LDO_OCP_FAULT_FLAG Set when LDO output current exceeds OCP condition Rising Edge N/A N/A Enabled (host must take action to disable the LDO if desired) N/A
IMAX_FAULT_FLAG Set when a an open is detected on IMAX pin Rising Edge Chareg disabled until Power-On-Reset N/A N/A N/A
MRWAKE1_TIMEOUT_FLAG Set when MR is low for at least tWAKE1 Rising Edge N/A N/A N/A N/A
MRWAKE2_TIMEOUT_FLAG Set when MR is low for at least tWAKE2 Rising Edge N/A N/A N/A N/A
MRRESET_WARN_FLAG Set when MR is low for at least tRESETWARN Rising Edge N/A N/A N/A N/A
TSHUT No flag. Die temperature exceeds thermal shutdown threshold is reached N/A Disabled Disabled Disabled Disabled