SLUSCK5 March   2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery without Input Source
      3. 8.3.3  Power Up from Input Source
        1. 8.3.3.1 Power Up REGN Regulation
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 Input Source Type Detection
          1. 8.3.3.3.1 PSEL Pins Sets Input Current Limit in bq25601
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Converter Power-Up
      4. 8.3.4  Boost Mode Operation From Battery
      5. 8.3.5  Host Mode and Standalone Power Management
        1. 8.3.5.1 Host Mode and Default Mode in bq25601
      6. 8.3.6  Power Path Management
      7. 8.3.7  Battery Charging Management
        1. 8.3.7.1  Autonomous Charging Cycle
        2. 8.3.7.2  Battery Charging Profile
        3. 8.3.7.3  Charging Termination
        4. 8.3.7.4  Thermistor Qualification
        5. 8.3.7.5  JEITA Guideline Compliance During Charging Mode
        6. 8.3.7.6  Boost Mode Thermistor Monitor during Battery Discharge Mode
        7. 8.3.7.7  Charging Safety Timer
        8. 8.3.7.8  Narrow VDC Architecture
        9. 8.3.7.9  Dynamic Power management
        10. 8.3.7.10 Supplement Mode
      8. 8.3.8  Shipping Mode and QON Pin
        1. 8.3.8.1 BATFET Disable Mode (Shipping Mode)
        2. 8.3.8.2 BATFET Enable (Exit Shipping Mode)
        3. 8.3.8.3 BATFET Full System Reset
        4. 8.3.8.4 QON Pin Operations
      9. 8.3.9  Status Outputs (PG, STAT, INT)
        1. 8.3.9.1 Power Good indicator (PG Pin and PG_STAT Bit)
        2. 8.3.9.2 Charging Status indicator (STAT)
        3. 8.3.9.3 Interrupt to Host (INT)
      10. 8.3.10 Protections
        1. 8.3.10.1 Voltage and Current Monitoring in Converter Operation
          1. 8.3.10.1.1 Voltage and Current Monitoring in Buck Mode
            1. 8.3.10.1.1.1 Input Overvoltage (ACOV)
            2. 8.3.10.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.3.10.2 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.2.1 VBUS Soft Start
          2. 8.3.10.2.2 VBUS Output Protection
          3. 8.3.10.2.3 Boost Mode Overvoltage Protection
        3. 8.3.10.3 Thermal Regulation and Thermal Shutdown
          1. 8.3.10.3.1 Thermal Protection in Buck Mode
          2. 8.3.10.3.2 Thermal Protection in Boost Mode
        4. 8.3.10.4 Battery Protection
          1. 8.3.10.4.1 Battery overvoltage Protection (BATOVP)
          2. 8.3.10.4.2 Battery Over-Discharge Protection
          3. 8.3.10.4.3 System Over-Current Protection
      11. 8.3.11 Serial interface
        1. 8.3.11.1 Data Validity
        2. 8.3.11.2 START and STOP Conditions
        3. 8.3.11.3 Byte Format
        4. 8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.11.5 Slave Address and Data Direction Bit
        6. 8.3.11.6 Single Read and Write
        7. 8.3.11.7 Multi-Read and Multi-Write
    4. 8.4 Register Maps
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
  9. Application and Implementation
    1. 9.1 Application information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 inductor Selection
        2. 9.2.2.2 input Capacitor
        3. 9.2.2.3 Output Capacitor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The bq25601 device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate drive.

Functional Block Diagram

bq25601 FBD_601_SLUSCK5.gif

Feature Description

Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (VBAT_DPL_RISE), the BATFET turns on and connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through BATFET (Supplement Mode). When the system is overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and set BATFET_DIS bit to indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET Enable (Exit Shipping Mode) is applied to re-enable BATFET.

Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power up sequence from input source is as listed:

  1. Power Up REGN LDO
  2. Poor Source Qualification
  3. Input Source Type Detection is based on or PSEL to set default input current limit (IINDPM) register or input source type.
  4. Input Voltage Limit Threshold Setting (VINDPM threshold)
  5. Converter Power-up

Power Up REGN Regulation

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN is enabled when all the below conditions are valid:

  • VVAC above VVAC_PRESENT
  • VVAC above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
  • After 220-ms delay is completed

If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.

Poor Source Qualification

After REGN LDO powers up, the device confirms the current capability of the input source. The input source must meet both of the following requirements in order to start the buck converter.

  • VBUS voltage below VVAC_OV
  • VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30 mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through or the PSEL pin. The bq25601 sets input current limit through PSEL pins.

After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following registers and pin are changed:

  1. Input Current Limit (IINDPM) register is changed to set current limit
  2. PG_STAT bit is set
  3. VBUS_STAT bit is updated to indicate USB or other input source

The host can over-write IINDPM register to change the input current limit if needed. The charger input current is always limited by the IINDPM register.

PSEL Pins Sets Input Current Limit in bq25601

The bq25601 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. When the device operates in host-control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When the device is in default mode, PSEL value updates IINDPM in real time.

Table 1. Input Current Limit Setting from PSEL

Input Detection PSEL Pin INPUT CURRENT LIMIT (ILIM) VBUS_STAT
USB SDP High 500 mA 001
Adapter Low 2.4A 011

Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 5.4V) for USBThe device's VINDPM is set at 4.5V. The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.

Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the device limits input current to the value set by IINDPM register.

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

The device switches to PFM control at light load or when battery is below minimum system voltage setting or charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA output requirement. The maximum output current is up to 1.2 A. The boost operation can be enabled if the conditions are valid:

  1. BAT above VOTG_BAT
  2. VBUS less than BAT+VSLEEP (in sleep mode)
  3. Boost mode operation is enabled (OTG_CONFIG bit = 1)
  4. Voltage at TS (thermistor) pin is within acceptable range (VBHOT < VTS < VBCOLD)
  5. After 30-ms delay from boost mode enable

During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V and the output current can reach up to 1.2 A, selected through I2C (BOOST_LIM bit). The boost output is maintained when BAT is above VOTG_BAT threshold.

When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

Host Mode and Standalone Power Management

Host Mode and Default Mode in bq25601

The bq25601 is a host controlled charger, but it can operate in default mode without host management. in default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode, WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM register changes.

in default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.

Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.

When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and BATFET_DIS bits.

bq25601 Watchdog_Flow_Chart_SLUSCJ4.gif Figure 10. Watchdog Timer Flow Chart

Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.

Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

Autonomous Charging Cycle

With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously completes a charging cycle without host involvement. The device default charging parameters are listed in Table 2. The host can always control the charging operations and optimize the charging parameters by writing to the corresponding registers through I2C.

Table 2. Charging Parameter Default Setting

Default Mode bq25601
Charging voltage 4.208V
Charging current 2.048 A
Pre-charge current 180 mA
Termination current 180 mA
Temperature profile JEITA
Safety timer 10 hours

A new charge cycle starts when the following conditions are valid:

  • Converter starts
  • Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
  • No thermistor fault on TS
  • No safety timer fault
  • BATFET is not forced to turn off (BATFET_DIS bit = 0)

The charger device automatically terminates the charging cycle when the charging current is below termination threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit can initiate a new charging cycle.

The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an INT is asserted to notify the host.

Battery Charging Profile

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and regulates current and voltage accordingly.

Table 3. Charging Current Setting

VBAT CHARGinG CURRENT REGISTER DEFAULT SETTinG CHRG_STAT
< 2.2 V ISHORT 100 mA 01
2.2 V to 3 V IPRECHG 180 mA 01
> 3 V ICHG 2.048 A 10

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. in this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

bq25601 Data_CCPD_SLUSCJ4.gif Figure 11. Battery Charging Profile

Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn on again to engage Supplement Mode.

When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host. Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

At low termination currents (25 mA-50 mA), due to the comparator offset, the actual termination current may be 10 mA-20 mA higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer can be applied after termination is detected. The termination timer will follow safety timer constraints, such that if safety timer is suspended, so will the termination timer. Similarly, if safety timer is doubled, so will the termination timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read CHRG_STAT and TOPOFF_ACTIVE to find out the termination status.

Top off timer gets reset at one of the following conditions:

  1. Charge disable to enable
  2. Termination status low to high
  3. REG_RST register bit is set

The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host when entering top-off timer segment as well as when top-off timer expires.

Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

JEITA Guideline Compliance During Charging Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges.

To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5 range.

At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V.

The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm temperature (T3-T5) can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool temperature (T1-T2) can be further reduced to 20% of fast charge current (JEITA_ISET).

bq25601 JEITA_current_slusck5.gif Figure 12. JEITA Profile: Charging Current
bq25601 JEITA_voltage_slusck5.gif Figure 13. JEITA Profile: Charging Voltage

Equation 1 through Equation 2 describe updates to the resistor bias network.

Equation 1. bq25601 eq_01_slusck5.gif
Equation 2. bq25601 eq_02_slusck5.gif

Select 0°C to 60°C range for Li-ion or Li-polymer battery:

  • RTHCOLD = 27.28 KΩ
  • RTHHOT = 3.02 KΩ
  • RT1 = 5.23 KΩ
  • RT2 = 30.9 KΩ

Boost Mode Thermistor Monitor during Battery Discharge Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the to thresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended. In additional, VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once temperature returns within thresholds, the boost mode is recovered and NTC_FAULT is cleared.

bq25601 TS_Pin_Thermistor_Sense_Threshold_in_Boost_Mode_SLUSCK6.gif Figure 14. TS Pin Thermistor Sense Threshold in Boost Mode

Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher than VBATLOWV threshold.

The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be disabled through I2C by setting EN_TIMER bit

During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).

Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.

When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the system is always regulated at typically 50mV above battery voltage. The status register VSYS_STAT bit goes high when the system is in minimum system voltage regulation.

bq25601 D002_SLUSCJ4.gif Figure 15. System Voltage vs Battery Voltage

Dynamic Power management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (IIDPM) or the voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode, the status register bits VDPM_STAT (VINDPM) or IDPM_STAT (IINDPM) goes high. Figure 16 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V minimum system voltage setting.

bq25601 DPM_Repsonse_SLUSCJ4.gif Figure 16. DPM Response

Supplement Mode

When the system voltage falls 180 mV (VBAT > VSYSMin) or 45 mV (VBAT < VSYSMin) below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode.

As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Figure 17 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.

bq25601 D001_SLUSCJ4.gif Figure 17. BAFET V-I Curve

Shipping Mode and QON Pin

BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configured by BATFET_DLY bit.

BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following events can enable BATFET to restore system power:

  1. Plug in adapter
  2. Clear BATFET_DIS bit
  3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
  4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping mode

BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not pluggeD–in. By changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a power-on-reset. The QON pin supports push-button interface to reset system power without host by changing the state of BATFET.

When the QON pin is driven to logic low for tQON_RST while input source is not plugged in and BATFET is enabled (BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0.

QON Pin Operations

The QON pin incorporates two functions to control BATFET.

  1. BATFET Enable: A QON logic transition from high to low with longer than tSHIPMODE deglitch turns on BATFET and exit shipping mode
  2. BATFET Reset: When QON is driven to logic low by at least tQON_RST while adapter is not plugged in (and BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST. The BATFET is re-enabled after tBATFET_RST duration. This function allows systems connected to SYS to have power-on-reset. This function can be disabled by setting BATFET_RST_EN bit to 0.

Figure 18 shows the sample external configurations for each.

bq25601 App_Cir_Config_EEQONHIZ_SLUSCJ4.gif Figure 18. QON Timing
bq25601 App_Cir_Config_part2_SLUSCK5.gif Figure 19. QON Circuit

Status Outputs (PG, STAT, INT)

Power Good indicator (PG Pin and PG_STAT Bit)

The PG_STAT bit goes HIGH and PG pin goes LOW to indicate a good input source when:

  • VBUS above VVBUS_UVLO
  • VBUS above battery (not in sleep)
  • VBUS below VVAC_OV threshold
  • VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  • Completed input Source Type Detection

Charging Status indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin function can be disabled by setting the EN_ICHG_MON bits = 11.

Table 4. STAT Pin State

CHARGING STATE STAT INDICATOR
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)
Boost Mode suspend (due to TS fault)
Blinking at 1 Hz

Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system on the device operation. The following events will generate 256-μs INT pulse.

  • USB/adapter source identified (through PSEL detection)
  • Good input source detected
    • VBUS above battery (not in sleep)
    • VBUS below VVAC_OV threshold
    • VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  • input removed
  • Charge Complete
  • Any FAULT event in REG09
  • VINDPM / IINDPM event detected (maskable)

When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively. The first read reports the pre-existing fault register status and the second read reports the current fault register status.

Protections

Voltage and Current Monitoring in Converter Operation

The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and boost mode operation.

Voltage and Current Monitoring in Buck Mode

Input Overvoltage (ACOV)

If VBUS voltage exceeds VVAC_OV (programmable via OVP[2:0] bits), the device stops switching immediately.

During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host. The device will automatically resume normal operation once the input voltage drops back below the OVP threshold.

System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation voltage when the system is regulate at VSYSMIN. Upon SYSOVP, converter stops switching immediately to clamp the overshoot. The charger provides 30 mA discharge current to bring down the system voltage.

Voltage and Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode operation.

VBUS Soft Start

When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.

VBUS Output Protection

The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage protection. The Boost build in accurate constant current regulation to allow OTG to adaptive to various types of load. If short circuit is detected on VBUS, the Boost turns off and retry 7 times. If retries are not successful, OTG is disabled with OTG_CONFIG bit cleared. In addition, the BOOST_FAULT bit is set and INT pulse is generated. The BOOST_FAULT bit can be cleared by host by re-enabling boost mode

Boost Mode Overvoltage Protection

When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage protection which stops switching, clears OTG_CONFIG bit and exits boost mode. At Boost overvoltage duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to the host.

Thermal Regulation and Thermal Shutdown

Thermal Protection in Buck Mode

The bq25601 monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface temperature exceeds TSHUT(160ºC). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the host. The BATFET and converter is enabled to recover when IC temperature is TSHUT_HYS (30ºC) below TSHUT(160ºC).

Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC junction temperature exceeds TSHUT (160ºC), the boost mode is disabled by setting OTG_CONFIG bit low and BATFET is turned off. When IC junction temperature is below TSHUT(160ºC) - TSHUT_HYS (30ºC), the BATFET is enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.

Battery Protection

Battery overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an INT is asserted to the host.

Battery Over-Discharge Protection

When battery is discharged below VBAT_DPL_FALL, the BATFET is turned off to protect battery from over discharge. To recover from over-discharge latch-off, an input source plug-in is required at VBUS. The battery is charged with ISHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set in IPRECHG register when the battery voltage is between VSHORTZ and VBAT_LOWV.

System Over-Current Protection

When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET overcurrent limit, the BATFET latches off. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off condition and turn on BATFET.

Serial interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG0B. Register read beyond REG0B (0x0B) returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

bq25601 Bit_Trans_I2C_SLUSCJ4.gif Figure 20. Bit Transfer on the I2C Bus

START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the mAster. The bus is considered busy after the START condition, and free after the STOP condition.

bq25601 TS_Start_Stop_SLUSCJ4.gif Figure 21. TS START and STOP conditions

Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the mAster into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

bq25601 Data_Transfer_I2C_Bus_SLUSCJ4.gif Figure 22. Data Transfer on the I2C Bus

Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge ninth clock pulse, are generated by the mAster. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The mAster can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

bq25601 Complete_Data_Transfer_SLUSCJ4.gif Figure 23. Complete Data Transfer

Single Read and Write

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

bq25601 Single_Write_SLUSCJ4.gif Figure 24. Single Write
bq25601 Single_Read_SLUSCJ4.gif Figure 25. Single Read

Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG0B.

bq25601 Multi-Write_SLUSCJ4.gif Figure 26. Multi-Write
bq25601 Multi-Read_SLUSCJ4.gif Figure 27. Multi-Read

REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and multi-write.

Register Maps

I2C Slave Address: 6BH

REG00

Table 5. REG00 Field Descriptions

Bit Field POR Type Reset Description Comment
7 EN_HIZ 0 R/W by REG_RST
by Watchdog
0 – Disable, 1 – Enable Enable HIZ Mode
0 – Disable (default)
1 – Enable
6 EN_ICHG_MON[1] 0 R/W by REG_RST 00 - Enable STAT pin function (default)
01 - Reserved
10 - Reserved

11 - Disable STAT pin function (float pin)
5 EN_ICHG_MON[0] 0 R/W by REG_RST
4 IINDPM[4] 1 R/W by REG_RST 1600 mA Input Current Limit
Offset: 100 mA
Range: 100 mA (000000) – 3.2 A (11111)
Default:2400 mA (10111), maximum input current limit, not typical.
IINDPM bits are changed automatically after input source detection is completed


PSEL = Hi = 500 mA
PSEL = Lo = 2.4 A
Host can over-write IINDPM register bits after input source detection is completed.
3 IINDPM[3] 0 R/W by REG_RST 800 mA
2 IINDPM[2] 1 R/W by REG_RST 400 mA
1 IINDPM[1] 1 R/W by REG_RST 200 mA
0 IINDPM[0] 1 R/W by REG_RST 100 mA
LEGEND: R/W = Read/Write; R = Read only

REG01

Table 6. REG01 Field Descriptions

Bit Field POR Type Reset Description Comment
7 PFM _DIS 0 R/W by REG_RST 0 – Enable PFM
1 – Disable PFM
Default: 0 - Enable
6 WD_RST 0 R/W by REG_RST
by Watchdog
I2C Watchdog Timer Reset 0 – Normal ; 1 – Reset Default: Normal (0) Back to 0 after watchdog timer reset
5 OTG_CONFIG 0 R/W by REG_RST
by Watchdog
0 – OTG Disable
1 – OTG Enable
Default: OTG disable (0)
Note:
1. OTG_CONFIG would over-ride Charge Enable Function in CHG_CONFIG
4 CHG_CONFIG 1 R/W by REG_RST
by Watchdog
0 - Charge Disable
1- Charge Enable
Default: Charge Battery (1)
Note:
1. Charge is enabled when both CE pin is pulled low AND CHG_CONFIG bit is 1.
3 SYS_Min[2] 1 R/W by REG_RST System Minimum Voltage
000: 2.6 V
001: 2.8 V
010: 3 V
011: 3.2 V
100: 3.4 V
101: 3.5 V
110: 3.6 V
111: 3.7 V
Default: 3.5 V (101)
2 SYS_Min[1] 0 R/W by REG_RST
1 SYS_Min[0] 1 R/W by REG_RST
0 Min_VBAT_SEL 0 R/W by REG_RST 0 – 2.8 V BAT falling,
1 – 2.5 V BAT falling
Minimum battery voltage for OTG mode. Default falling 2.8 V (0); Rising threshold 3.0 V (0)
LEGEND: R/W = Read/Write; R = Read only

REG02

Table 7. REG02 Field Descriptions

Bit Field POR Type Reset Description Comment
7 BOOST_LIM 1 R/W by REG_RST
by Watchdog
0 = 0.5 A
1 = 1.2 A
Default: 1.2 A (1)
Note:
The current limit options listed are minimum current limit specs.
6 Q1_FULLON 0 R/W by REG_RST 0 – Use higher Q1 RDSON when programmed IINDPM < 700mA (better accuracy)
1 – Use lower Q1 RDSON always (better efficiency)
In boost mode, full FET is always used and this bit has no effect
5 ICHG[5] 1 R/W by REG_RST
by Watchdog
1920 mA Fast Charge Current
Default: 2040mA (100010)

Range: 0 mA (0000000) – 3000 mA (110010)
Note:
ICHG = 0 mA disables charge.
ICHG > 3000 mA (110010 clamped to register value 3000 mA (110010))
4 ICHG[4] 0 R/W by REG_RST
by Watchdog
960 mA
3 ICHG[3] 0 R/W by REG_RST
by Watchdog
480 mA
2 ICHG[2] 0 R/W by REG_RST
by Watchdog
240 mA
1 ICHG[1] 1 R/W by REG_RST
by Watchdog
120 mA
0 ICHG[0] 0 R/W by REG_RST
by Watchdog
60 mA
LEGEND: R/W = Read/Write; R = Read only

REG03

Table 8. REG03 Field Descriptions

Bit Field POR Type Reset Description Comment
7 IPRECHG[3] 0 R/W by REG_RST
by Watchdog
480 mA Precharge Current
Default: 180 mA (0010)
Offset: 60 mA

Note: IPRECHG > 780 mA clamped to 780 mA (1100)
6 IPRECHG[2] 0 R/W by REG_RST
by Watchdog
240 mA
5 IPRECHG[1] 1 R/W by REG_RST
by Watchdog
120 mA
4 IPRECHG[0] 0 R/W by REG_RST
by Watchdog
60 mA
3 ITERM[3] 0 R/W by REG_RST
by Watchdog
480 mA Termination Current
Default: 180 mA (0010)
Offset: 60 mA

2 ITERM[2] 0 R/W by REG_RST
by Watchdog
240 mA
1 ITERM[1] 1 R/W by REG_RST
by Watchdog
120 mA
0 ITERM[0] 0 R/W by REG_RST
by Watchdog
60 mA
LEGEND: R/W = Read/Write; R = Read only

REG04

Table 9. REG04 Field Descriptions

Bit Field POR Type Reset Description Comment
7 VREG[4] 0 R/W by REG_RST
by Watchdog
512 mV

Charge Voltage

Offset: 3.856 V

Range: 3.856 V to 4.624 V (11000)

Default: 4.208 V (01011)

Special Value:

(01111): 4.352 V

Note: Value above 11000 (4.624 V) is clamped to  register value 11000 (4.624 V)
6 VREG[3] 1 R/W by REG_RST
by Watchdog
256 mV
5 VREG[2] 0 R/W by REG_RST
by Watchdog
128 mV
4 VREG[1] 1 R/W by REG_RST
by Watchdog
64 mV
3 VREG[0] 1 R/W by REG_RST
by Watchdog
32 mV
2 TOPOFF_TIMER[1] 0 R/W by REG_RST
by Watchdog
00 – Disabled (Default)
01 – 15 minutes
10 – 30 minutes
11 – 45 minutes
The extended time following the termination condition is met. When disabled, charge terminated when termination conditions are met
1 TOPOFF_TIMER[0] 0 R/W by REG_RST
by Watchdog
0 VRECHG 0 R/W by REG_RST
by Watchdog
0 – 100 mV
1 – 200 mV

Recharge threshold


Default: 100mV (0)
LEGEND: R/W = Read/Write; R = Read only

REG05

Table 10. REG05 Field Descriptions

Bit Field POR Type Reset Description Comment
7 EN_TERM 1 R/W by REG_RST
by Watchdog
0 – Disable
1 – Enable
Default: Enable termination (1)
6 Reserved 0 R/W by REG_RST
by Watchdog
Reserved Reserved
5 WATCHDOG[1] 0 R/W by REG_RST
by Watchdog
00 – Disable timer, 01 – 40 s, 10 – 80 s,11 – 160 s Default: 40 s (01)
4 WATCHDOG[0] 1 R/W by REG_RST
by Watchdog
3 EN_TIMER 1 R/W by REG_RST
by Watchdog
0 – Disable
1 – Enable both fast charge and precharge timer
Default: Enable (1)
2 CHG_TIMER 1 R/W by REG_RST
by Watchdog
0 – 5 hrs
1 – 10 hrs
Default: 10 hours (1)
1 TREG 1 R/W by REG_RST
by Watchdog
Thermal Regulation Threshold:
0 - 90°C
1 - 110°C
Default: 110°C (1)
0 JEITA_ISET
(0C-10C)
1 R/W by REG_RST
by Watchdog
0 – 50% of ICHG
1 – 20% of ICHG
Default: 20% (1)
LEGEND: R/W = Read/Write; R = Read only

REG06

Table 11. REG06 Field Descriptions

Bit Field POR Type Reset Description Comment
7 OVP[1] 0 R/W by REG_RST Default: 6.5V (01) VAC OVP threshold:
00 - 5.5 V
01 – 6.5 V (5-V input)
10 – 10.5 V (9-V input)
11 – 14 V (12-V input)
6 OVP[0] 1 R/W by REG_RST
5 BOOSTV[1] 1 R/W by REG_RST Boost Regulation Voltage:
00 - 4.85V
01 - 5.00V
10 - 5.15V
11 - 5.30V
4 BOOSTV[0] 0 R/W by REG_RST
3 VINDPM[3] 0 R/W by REG_RST 800 mV Absolute VINDPM Threshold Offset: 3.9 V
Range: 3.9 V (0000) – 5.4 V (1111)
Default: 4.5V (0110)
2 VINDPM[2] 1 R/W by REG_RST 400 mV
1 VINDPM[1] 1 R/W by REG_RST 200 mV
0 VINDPM[0] 0 R/W by REG_RST 100 mV
LEGEND: R/W = Read/Write; R = Read only

REG07

Table 12. REG07 Field Descriptions

Bit Field POR Type Reset Description Comment
7 IINDET_EN 0 R/W by REG_RST
by Watchdog

0 - Not in input current limit detection
1 - Force input current limit detection when VBUS is present
Returns to 0 after input detection is complete
6 TMR2X_EN 1 R/W by REG_RST
by Watchdog
0 – Disable
1 – Safety timer slowed by 2X during input DPM (both V and I) or JEITA cool, or thermal regulation
5 BATFET_DIS 0 R/W by REG_RST 0 – Allow Q4 turn on, 1 – Turn off Q4 with tBATFET_DLY delay time (REG07[3]) Default: Allow Q4 turn on(0)
4 JEITA_VSET
(45C-60C)
0 R/W by REG_RST
by Watchdog
0 – Set Charge Voltage to 4.1V ( max),
1 – Set Charge Voltage to VREG
3 BATFET_DLY 1 R/W by REG_RST 0 – Turn off BATFET immediately when BATFET_DIS bit is set
1 –Turn off BATFET after tBATFET_DLY (typ. 10 s) when BATFET_DIS bit is set
Default: 1
Turn off BATFET after tBATFET_DLY (typ. 10 s) when BATFET_DIS bit is set
2 BATFET_RST_EN 1 R/W by REG_RST
by Watchdog
0 – Disable BATFET reset function
1 – Enable BATFET reset function
Default: 1
Enable BATFET reset function
1 VDPM_BAT_TRACK[1] 0 R/W by REG_RST 00 - Disable function (VINDPM set by register)
01 - VBAT + 200mV
10 - VBAT + 250mV
11 - VBAT + 300mV
Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register value and VBAT + VDPM_BAT_TRACK
0 VDPM_BAT_TRACK[0] 0 R/W by REG_RST
LEGEND: R/W = Read/Write; R = Read only

REG08

Table 13. REG08 Field Descriptions

Bit Field POR Type Reset Description
7 VBUS_STAT[2] x R NA VBUS Status register

000: No input
001: USB Host SDP (500 mA) → PSEL HIGH
010: Adapter 2.4A → PSEL LOW
111: OTG
Software current limit is reported in IINDPM register
6 VBUS_STAT[1] x R NA
5 VBUS_STAT[0] x R NA
4 CHRG_STAT[1] x R NA Charging status:
00 – Not Charging
01 – Pre-charge (< VBATLOWV)
10 – Fast Charging
11 – Charge Termination
3 CHRG_STAT[0] x R NA
2 PG_STAT x R NA Power Good status:
0 – Power Not Good
1 – Power Good
1 THERM_STAT x R NA 0 – Not in ther mAl regulation
1 – in ther mAl regulation
0 VSYS_STAT x R NA 0 – Not in VSYSMin regulation (BAT > VSYSMin)
1 – in VSYSMin regulation (BAT < VSYSMin)
LEGEND: R/W = Read/Write

REG09

Table 14. REG09 Field Descriptions

Bit Field POR Type Reset Description
7 WATCHDOG_FAULT x R NA 0 – Normal, 1- Watchdog timer expiration
6 BOOST_FAULT x R NA 0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any conditions that we cannot start boost function)
5 CHRG_FAULT[1] x R NA 00 – Normal, 01 – input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10 - Thermal shutdown, 11 – Charge Safety Timer Expiration
4 CHRG_FAULT[0] x R NA
3 BAT_FAULT x R NA 0 – Normal, 1 – BATOVP
2 NTC_FAULT[2] x R NA JEITA
000 – Normal, 010 – Warm, 011 – Cool, 101 – Cold, 110 – Hot (Buck mode)
000 – Normal, 101 – Cold, 110 – Hot (Boost mode)
1 NTC_FAULT[1] x R NA
0 NTC_FAULT[0] x R NA
LEGEND: R/W = Read/Write; R = Read only

REG0A

Table 15. REG0A Field Descriptions

Bit Field POR Type Reset Description
7 VBUS_GD x R NA 0 – Not VBUS attached,
1 – VBUS Attached
6 VINDPM_STAT x R NA 0 – Not in VINDPM, 1 – in VINDPM
5 IINDPM_STAT x R NA 0 – Not in IINDPM, 1 – in IINDPM
4 Reserved x R NA
3 TOPOFF_ACTIVE x R NA 0 – Top off timer not counting.
1 – Top off timer counting
2 ACOV_STAT x R NA 0 – Device is NOT in ACOV
1 – Device is in ACOV
1 VINDPM_INT_ MASK 0 R/W by REG_RST 0 - Allow VINDPM INT pulse
1 - Mask VINDPM INT pulse
0 IINDPM_INT_ MASK 0 R/W by REG_RST 0 - Allow IINDPM INT pulse
1 - Mask IINDPM INT pulse
LEGEND: R/W = Read/Write; R = Read only

REG0B

Table 16. REG0B Field Descriptions

Bit Field POR Type Reset Description
7 REG_RST 0 R/W NA Register reset
0 – Keep current register setting
1 – Reset to default register value and reset safety timer
Note: Bit resets to 0 after register reset is completed
6 PN[3] x R NA
bq25601 : 0010

5 PN[2] x R NA
4 PN[1] x R NA
3 PN[0] x R NA
2 Reserved x R NA
1 DEV_REV[1] x R NA
0 DEV_REV[0] x R NA
LEGEND: R/W = Read/Write; R = Read only