SLUSCK5 March   2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery without Input Source
      3. 8.3.3  Power Up from Input Source
        1. 8.3.3.1 Power Up REGN Regulation
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 Input Source Type Detection
          1. 8.3.3.3.1 PSEL Pins Sets Input Current Limit in bq25601
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Converter Power-Up
      4. 8.3.4  Boost Mode Operation From Battery
      5. 8.3.5  Host Mode and Standalone Power Management
        1. 8.3.5.1 Host Mode and Default Mode in bq25601
      6. 8.3.6  Power Path Management
      7. 8.3.7  Battery Charging Management
        1. 8.3.7.1  Autonomous Charging Cycle
        2. 8.3.7.2  Battery Charging Profile
        3. 8.3.7.3  Charging Termination
        4. 8.3.7.4  Thermistor Qualification
        5. 8.3.7.5  JEITA Guideline Compliance During Charging Mode
        6. 8.3.7.6  Boost Mode Thermistor Monitor during Battery Discharge Mode
        7. 8.3.7.7  Charging Safety Timer
        8. 8.3.7.8  Narrow VDC Architecture
        9. 8.3.7.9  Dynamic Power management
        10. 8.3.7.10 Supplement Mode
      8. 8.3.8  Shipping Mode and QON Pin
        1. 8.3.8.1 BATFET Disable Mode (Shipping Mode)
        2. 8.3.8.2 BATFET Enable (Exit Shipping Mode)
        3. 8.3.8.3 BATFET Full System Reset
        4. 8.3.8.4 QON Pin Operations
      9. 8.3.9  Status Outputs (PG, STAT, INT)
        1. 8.3.9.1 Power Good indicator (PG Pin and PG_STAT Bit)
        2. 8.3.9.2 Charging Status indicator (STAT)
        3. 8.3.9.3 Interrupt to Host (INT)
      10. 8.3.10 Protections
        1. 8.3.10.1 Voltage and Current Monitoring in Converter Operation
          1. 8.3.10.1.1 Voltage and Current Monitoring in Buck Mode
            1. 8.3.10.1.1.1 Input Overvoltage (ACOV)
            2. 8.3.10.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.3.10.2 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.2.1 VBUS Soft Start
          2. 8.3.10.2.2 VBUS Output Protection
          3. 8.3.10.2.3 Boost Mode Overvoltage Protection
        3. 8.3.10.3 Thermal Regulation and Thermal Shutdown
          1. 8.3.10.3.1 Thermal Protection in Buck Mode
          2. 8.3.10.3.2 Thermal Protection in Boost Mode
        4. 8.3.10.4 Battery Protection
          1. 8.3.10.4.1 Battery overvoltage Protection (BATOVP)
          2. 8.3.10.4.2 Battery Over-Discharge Protection
          3. 8.3.10.4.3 System Over-Current Protection
      11. 8.3.11 Serial interface
        1. 8.3.11.1 Data Validity
        2. 8.3.11.2 START and STOP Conditions
        3. 8.3.11.3 Byte Format
        4. 8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.11.5 Slave Address and Data Direction Bit
        6. 8.3.11.6 Single Read and Write
        7. 8.3.11.7 Multi-Read and Multi-Write
    4. 8.4 Register Maps
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
  9. Application and Implementation
    1. 9.1 Application information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 inductor Selection
        2. 9.2.2.2 input Capacitor
        3. 9.2.2.3 Output Capacitor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 29) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the proper layout.

  1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
  2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
  4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using thermal pad as the single ground connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
  5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
  6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
  7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  8. Ensure that the number and sizes of vias allow enough copper for a given current path.

See the EVM user's guide SLUUBL3 for the recommended component placement with trace and via locations. For the VQFN information, refer to SCBA017 and SLUA271.

Layout Example

bq25601 High_Frequency_Current_Path_SLUSCJ4.gif Figure 29. High Frequency Current Path
bq25601 layout_image_slusck5.png Figure 30. Layout Example