SLUSDF7A January   2020  – February 2022 BQ25616

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up From Battery Without Input Source
      3. 9.3.3 Power Up From Input Source
        1. 9.3.3.1 Power Up ACFET
        2. 9.3.3.2 Power Up REGN LDO
        3. 9.3.3.3 Poor Source Qualification
        4. 9.3.3.4 Input Source Type Detection (IINDPM Threshold)
          1. 9.3.3.4.1 D+/D– Detection Sets Input Current Limit
        5. 9.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        6. 9.3.3.6 Power Up Converter in Buck Mode
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Standalone Charger
      6. 9.3.6 Power Path Management
        1. 9.3.6.1 Narrow VDC Architecture
        2. 9.3.6.2 Dynamic Power Management
        3. 9.3.6.3 Supplement Mode
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
          1. 9.3.7.4.1 JEITA Guideline Compliance During Charging Mode (BQ25616J)
          2. 9.3.7.4.2 Hot/Cold Temperature Window During Charging Mode (BQ25616)
          3. 9.3.7.4.3 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 9.3.7.5 Charging Safety Timer
      8. 9.3.8 Status Outputs ( PG, STAT)
        1. 9.3.8.1 Power Good Indicator ( PG Pin )
        2. 9.3.8.2 Charging Status Indicator (STAT)
      9. 9.3.9 Protections
        1. 9.3.9.1 Input Current Limit
        2. 9.3.9.2 Voltage and Current Monitoring in Buck Mode
          1. 9.3.9.2.1 Input Overvoltage Protection (ACOV)
          2. 9.3.9.2.2 System Overvoltage Protection (SYSOVP)
        3. 9.3.9.3 Voltage and Current Monitoring in Boost Mode
          1. 9.3.9.3.1 Boost Mode Overvoltage Protection
        4. 9.3.9.4 Thermal Regulation and Thermal Shutdown
          1. 9.3.9.4.1 Thermal Protection in Buck Mode
          2. 9.3.9.4.2 Thermal Protection in Boost Mode
        5. 9.3.9.5 Battery Protection
          1. 9.3.9.5.1 Battery Overvoltage Protection (BATOVP)
          2. 9.3.9.5.2 Battery Overdischarge Protection
          3. 9.3.9.5.3 System Overcurrent Protection
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 BQ25616/616J Application without External OVP
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Inductor Selection
          2. 10.2.1.2.2 Input Capacitor and Resistor
          3. 10.2.1.2.3 Output Capacitor
        3. 10.2.1.3 Application Curves
      2. 10.2.2 BQ25616/616J Application with External OVP
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

Figure 7-1 RTW Package24-Pin WQFNTop View
Table 7-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
ACDRV 2 AO Charge pump output to drive external N-channel MOSFET (ACFET). It provides 6V voltage above VBUS as gate drive to turn on ACFET when VAC voltage is below ACOV threshold (14.2-V) and above UVLO. Leave ACDRV floating if external OVP is not being used.
BAT 13 P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF(2) closely to the BAT pin.
14
BTST 21 P PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor(2) from SW to BTST.
CE 9 DI Charge enable pin. When this pin is driven LOW, battery charging is enabled.
D+ 3 AIO Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors
D– 4 AIO Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors
GND 17 P Power ground and signal ground
18
ICHG 10 AI ICHG pin sets the charge current limit. A resistor is connected from ICHG pin to ground to set charge current limit as ICHG = KICHG/RICHG. The acceptable range for charge current is 300 mA – 3000 mA.
ILIM 8 AI ILIM sets the input current limit when the input adapter is detected as unknown. Otherwise, the input current limit is set by D+/D– detection outcome. A resistor is connected from ILIM pin to ground to set the input current limit as IINDPM = KILIM/RILIM. The acceptable range for ILIM current is 500 mA - 3200 mA.
OTG 6 DI Boost mode enable pin. When this pin is pulled HIGH, boost mode is enabled. OTG pin cannot be floating.
PG 7 DO Open drain active low power good indicator. Connect to the pull up rail through 10 kΩ resistor. LOW indicates a good input if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and input current limit is above 30 mA.
PMID 23 P Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Place a 10-µF capacitor(2) on PMID to GND.
REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boot-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor(2) from REGN to analog GND. The capacitor should be placed close to the IC.
STAT 5 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1Hz
SW 19 P Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
20
SYS 15 P System output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF (min) capacitor(2) close to the SYS pin.
16
TS 11 AI Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge and boost mode suspend when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor. BQ25616 supports hot/cold profile and BQ25616J supports JEITA profile.
VAC 1 P Charger input voltage sensing. Optional external n-channel ACFET is placed between VAC and VBUS. When VAC voltage is below ACOV threshold (14.2-V) and above UVLO, ACFET turns on to connect VAC to VBUS, and power up the charger IC. Connect VAC and VBUS if ACFET is not to be used.
VBUS 24 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor(2) from VBUS to GND and place it as close as possible to the device.
VSET 12 AI VSET pin sets default battery charge voltage . Program battery regulation voltage with a resistor pull-down from VSET to GND.
RVSET > 50kΩ (float pin) = 4.208 V
RVSET < 500Ω (short to GND) = 4.352 V
5kΩ < RVSET < 25kΩ = 4.100 V
Thermal Pad — P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power
(2) All capacitors are ceramic unless otherwise specified