SLUSDU3 May 2021 BQ25720
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADC_CONV | ADC_START | ADC_FULLSCALE | PTM_EXIT_LIGHT_LOAD | Reserved | |||
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_ADC_CMPIN | EN_ADC_VBUS | EN_ADC_PSYS | EN_ADC_IIN | EN_ADC_IDCHG | EN_ADC_ICHG | EN_ADC_VSYS | EN_ADC_VBAT |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC is disabled in low power mode. Before enabling ADC, low power mode should be disabled first.
SMBus BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
15 | ADC_CONV | R/W | 0b | Typical each ADC channel
conversion time is 25 ms maximum. Total ADC conversion time is the
product of 25ms and enabled channel counts. 0b: One-shot update. Do one set of conversion updates to registers REG0x23(), REG0x24(), REG0x25(), and REG0x26() after ADC_START = 1. 1b: Continuous update. Do a set of conversion updates to registers REG0x23(), REG0x24(), REG0x25(), and REG0x26() every 1 sec. |
14 | ADC_START | R/W | 0b | 0b: No ADC conversion 1b: Start ADC conversion. After the one-shot update is complete, this bit automatically resets to zero |
13 | ADC_FULLSCALE | R/W | 1b | ADC input voltage range adjustment for PSYS and CMPIN ADC Channels. 2.04V full scale holds 8mV/LSB resolution and 3.06V full scale holds 12mV/LSB resolution 0b: 2.04 V 1b: 3.06 V <default at POR>(Not accurate for REGN<6V application (VBUS & VSYS< 6V) ) |
12 | PTM_EXIT_LIGHT_LOAD | R/W | 0b |
PTM Mode Auto Exit Enable When this bit is HIGH, under PTM mode operation when input current is lower than 150mA(10mΩ input sensing resistor)/300mA(5mΩ input sensing resistor) for more than 500us, charger should temporary exit PTM mode and return to buck-boost mode operation. When input current increase back to be higher than 200mA(10mΩ input sensing resistor)/400mA(5mΩ input sensing resistor) for more than 500us, the charger should automatically return to PTM operation. 0b: Disable <default at POR> 1b: Enable |
11-8 | Reserved | R/W | 0000b | Reserved |
SMBus BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | EN_ADC_CMPIN | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
6 | EN_ADC_VBUS | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
5 | EN_ADC_PSYS | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
4 | EN_ADC_IIN | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
3 | EN_ADC_IDCHG | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
2 | EN_ADC_ICHG | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
1 | EN_ADC_VSYS | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |
0 | EN_ADC_VBAT | R/W | 0b | 0b: Disable <default at POR> 1b: Enable |