SLUSDF9 June   2020 BQ25790

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
      1.      Device Images
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Dual-Input Power Mux
        1. 8.3.3.1 VBUS Input Only
        2. 8.3.3.2 One ACFET-RBFET
        3. 8.3.3.3 Two ACFETs-RBFETs
      4. 8.3.4  Device Power Up from Battery without Input Source
      5. 8.3.5  Device Power Up from Input Source
        1. 8.3.5.1 Power Up REGN LDO
        2. 8.3.5.2 Poor Source Qualification
        3. 8.3.5.3 Input Source Type Detection
          1. 8.3.5.3.1 D+/D– Detection Sets Input Current Limit
          2. 8.3.5.3.2 Force Input Current Limit Detection
          3. 8.3.5.3.3 Connector Fault Detection
        4. 8.3.5.4 Input Current Optimizer (ICO)
        5. 8.3.5.5 Default VINDPM Setting
        6. 8.3.5.6 Device HIZ State
        7. 8.3.5.7 ILIM_HIZ Pin
        8. 8.3.5.8 IBAT Pin for Battery Current Sensing
        9. 8.3.5.9 Buck-Boost Converter Operation
          1. 8.3.5.9.1 Pulse Frequency Modulation (PFM)
      6. 8.3.6  USB On-The-Go (OTG)
        1. 8.3.6.1 OTG Mode to Power External Devices
      7. 8.3.7  Power Path Management
        1. 8.3.7.1 Narrow VDC Architecture
        2. 8.3.7.2 Dynamic Power Management
      8. 8.3.8  Battery Charging Management
        1. 8.3.8.1 Autonomous Charging Cycle
        2. 8.3.8.2 Battery Charging Profile
        3. 8.3.8.3 Charging Termination
        4. 8.3.8.4 Charging Safety Timer
        5. 8.3.8.5 Thermistor Qualification
          1. 8.3.8.5.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.8.5.2 Cold/Hot Temperature Window in OTG Mode
      9. 8.3.9  Integrated 16-Bit ADC for Monitoring
      10. 8.3.10 Status Outputs (PG, STAT, and INT)
        1. 8.3.10.1 Power Good Indicator (PG)
        2. 8.3.10.2 Charging Status Indicator (STAT Pin)
        3. 8.3.10.3 Interrupt to Host (INT)
      11. 8.3.11 Ship FET Control
        1. 8.3.11.1 Shutdown Mode
        2. 8.3.11.2 Ship Mode
        3. 8.3.11.3 System Power Reset
      12. 8.3.12 Protections
        1. 8.3.12.1 Voltage and Current Monitoring
        2. 8.3.12.2 Thermal Regulation and Thermal Shutdown
      13. 8.3.13 Serial Interface
        1. 8.3.13.1 Data Validity
        2. 8.3.13.2 START and STOP Conditions
        3. 8.3.13.3 Byte Format
        4. 8.3.13.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.13.5 Slave Address and Data Direction Bit
        6. 8.3.13.6 Single Write and Read
        7. 8.3.13.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
        1. 8.5.1.1  REG00_Minimal_System_Voltage Register (Offset = 0h) [reset = X]
          1. Table 10. REG00_Minimal_System_Voltage Register Field Descriptions
        2. 8.5.1.2  REG01_Charge_Voltage_Limit Register (Offset = 1h) [reset = X]
          1. Table 11. REG01_Charge_Voltage_Limit Register Field Descriptions
        3. 8.5.1.3  REG03_Charge_Current_Limit Register (Offset = 3h) [reset = X]
          1. Table 12. REG03_Charge_Current_Limit Register Field Descriptions
        4. 8.5.1.4  REG05_Input_Voltage_Limit Register (Offset = 5h) [reset = 24h]
          1. Table 13. REG05_Input_Voltage_Limit Register Field Descriptions
        5. 8.5.1.5  REG06_Input_Current_Limit Register (Offset = 6h) [reset = 12Ch]
          1. Table 14. REG06_Input_Current_Limit Register Field Descriptions
        6. 8.5.1.6  REG08_Precharge_Control Register (Offset = 8h) [reset = C3h]
          1. Table 15. REG08_Precharge_Control Register Field Descriptions
        7. 8.5.1.7  REG09_Termination_Control Register (Offset = 9h) [reset = 5h]
          1. Table 16. REG09_Termination_Control Register Field Descriptions
        8. 8.5.1.8  REG0A_Re-charge_Control Register (Offset = Ah) [reset = X]
          1. Table 17. REG0A_Re-charge_Control Register Field Descriptions
        9. 8.5.1.9  REG0B_VOTG_regulation Register (Offset = Bh) [reset = DCh]
          1. Table 18. REG0B_VOTG_regulation Register Field Descriptions
        10. 8.5.1.10 REG0D_IOTG_regulation Register (Offset = Dh) [reset = 4Bh]
          1. Table 19. REG0D_IOTG_regulation Register Field Descriptions
        11. 8.5.1.11 REG0E_Timer_Control Register (Offset = Eh) [reset = 3Dh]
          1. Table 20. REG0E_Timer_Control Register Field Descriptions
        12. 8.5.1.12 REG0F_Charger_Control_0 Register (Offset = Fh) [reset = A2h]
          1. Table 21. REG0F_Charger_Control_0 Register Field Descriptions
        13. 8.5.1.13 REG10_Charger_Control_1 Register (Offset = 10h) [reset = 85h]
          1. Table 22. REG10_Charger_Control_1 Register Field Descriptions
        14. 8.5.1.14 REG11_Charger_Control_2 Register (Offset = 11h) [reset = 40h]
          1. Table 23. REG11_Charger_Control_2 Register Field Descriptions
        15. 8.5.1.15 REG12_Charger_Control_3 Register (Offset = 12h) [reset = 0h]
          1. Table 24. REG12_Charger_Control_3 Register Field Descriptions
        16. 8.5.1.16 REG13_Charger_Control_4 Register (Offset = 13h) [reset = X]
          1. Table 25. REG13_Charger_Control_4 Register Field Descriptions
        17. 8.5.1.17 REG14_Charger_Control_5 Register (Offset = 14h) [reset = 16h]
          1. Table 26. REG14_Charger_Control_5 Register Field Descriptions
        18. 8.5.1.18 REG15_Reserved Register (Offset = 15h) [reset = 00h]
          1. Table 27. REG15_Reserved Register Field Descriptions
        19. 8.5.1.19 REG16_Temperature_Control Register (Offset = 16h) [reset = C0h]
          1. Table 28. REG16_Temperature_Control Register Field Descriptions
        20. 8.5.1.20 REG17_NTC_Control_0 Register (Offset = 17h) [reset = 7Ah]
          1. Table 29. REG17_NTC_Control_0 Register Field Descriptions
        21. 8.5.1.21 REG18_NTC_Control_1 Register (Offset = 18h) [reset = 54h]
          1. Table 30. REG18_NTC_Control_1 Register Field Descriptions
        22. 8.5.1.22 REG19_ICO_Current_Limit Register (Offset = 19h) [reset = 0h]
          1. Table 31. REG19_ICO_Current_Limit Register Field Descriptions
        23. 8.5.1.23 REG1B_Charger_Status_0 Register (Offset = 1Bh) [reset = 0h]
          1. Table 32. REG1B_Charger_Status_0 Register Field Descriptions
        24. 8.5.1.24 REG1C_Charger_Status_1 Register (Offset = 1Ch) [reset = 0h]
          1. Table 33. REG1C_Charger_Status_1 Register Field Descriptions
        25. 8.5.1.25 REG1D_Charger_Status_2 Register (Offset = 1Dh) [reset = 0h]
          1. Table 34. REG1D_Charger_Status_2 Register Field Descriptions
        26. 8.5.1.26 REG1E_Charger_Status_3 Register (Offset = 1Eh) [reset = 0h]
          1. Table 35. REG1E_Charger_Status_3 Register Field Descriptions
        27. 8.5.1.27 REG1F_Charger_Status_4 Register (Offset = 1Fh) [reset = 0h]
          1. Table 36. REG1F_Charger_Status_4 Register Field Descriptions
        28. 8.5.1.28 REG20_FAULT_Status_0 Register (Offset = 20h) [reset = 0h]
          1. Table 37. REG20_FAULT_Status_0 Register Field Descriptions
        29. 8.5.1.29 REG21_FAULT_Status_1 Register (Offset = 21h) [reset = 0h]
          1. Table 38. REG21_FAULT_Status_1 Register Field Descriptions
        30. 8.5.1.30 REG22_Charger_Flag_0 Register (Offset = 22h) [reset = 0h]
          1. Table 39. REG22_Charger_Flag_0 Register Field Descriptions
        31. 8.5.1.31 REG23_Charger_Flag_1 Register (Offset = 23h) [reset = 0h]
          1. Table 40. REG23_Charger_Flag_1 Register Field Descriptions
        32. 8.5.1.32 REG24_Charger_Flag_2 Register (Offset = 24h) [reset = 0h]
          1. Table 41. REG24_Charger_Flag_2 Register Field Descriptions
        33. 8.5.1.33 REG25_Charger_Flag_3 Register (Offset = 25h) [reset = 0h]
          1. Table 42. REG25_Charger_Flag_3 Register Field Descriptions
        34. 8.5.1.34 REG26_FAULT_Flag_0 Register (Offset = 26h) [reset = 0h]
          1. Table 43. REG26_FAULT_Flag_0 Register Field Descriptions
        35. 8.5.1.35 REG27_FAULT_Flag_1 Register (Offset = 27h) [reset = 0h]
          1. Table 44. REG27_FAULT_Flag_1 Register Field Descriptions
        36. 8.5.1.36 REG28_Charger_Mask_0 Register (Offset = 28h) [reset = 0h]
          1. Table 45. REG28_Charger_Mask_0 Register Field Descriptions
        37. 8.5.1.37 REG29_Charger_Mask_1 Register (Offset = 29h) [reset = 0h]
          1. Table 46. REG29_Charger_Mask_1 Register Field Descriptions
        38. 8.5.1.38 REG2A_Charger_Mask_2 Register (Offset = 2Ah) [reset = 0h]
          1. Table 47. REG2A_Charger_Mask_2 Register Field Descriptions
        39. 8.5.1.39 REG2B_Charger_Mask_3 Register (Offset = 2Bh) [reset = 0h]
          1. Table 48. REG2B_Charger_Mask_3 Register Field Descriptions
        40. 8.5.1.40 REG2C_FAULT_Mask_0 Register (Offset = 2Ch) [reset = 0h]
          1. Table 49. REG2C_FAULT_Mask_0 Register Field Descriptions
        41. 8.5.1.41 REG2D_FAULT_Mask_1 Register (Offset = 2Dh) [reset = 0h]
          1. Table 50. REG2D_FAULT_Mask_1 Register Field Descriptions
        42. 8.5.1.42 REG2E_ADC_Control Register (Offset = 2Eh) [reset = 30h]
          1. Table 51. REG2E_ADC_Control Register Field Descriptions
        43. 8.5.1.43 REG2F_ADC_Function_Disable_0 Register (Offset = 2Fh) [reset = 0h]
          1. Table 52. REG2F_ADC_Function_Disable_0 Register Field Descriptions
        44. 8.5.1.44 REG30_ADC_Function_Disable_1 Register (Offset = 30h) [reset = 0h]
          1. Table 53. REG30_ADC_Function_Disable_1 Register Field Descriptions
        45. 8.5.1.45 REG31_IBUS_ADC Register (Offset = 31h) [reset = 0h]
          1. Table 54. REG31_IBUS_ADC Register Field Descriptions
        46. 8.5.1.46 REG33_IBAT_ADC Register (Offset = 33h) [reset = 0h]
          1. Table 55. REG33_IBAT_ADC Register Field Descriptions
        47. 8.5.1.47 REG35_VBUS_ADC Register (Offset = 35h) [reset = 0h]
          1. Table 56. REG35_VBUS_ADC Register Field Descriptions
        48. 8.5.1.48 REG37_VAC1_ADC Register (Offset = 37h) [reset = 0h]
          1. Table 57. REG37_VAC1_ADC Register Field Descriptions
        49. 8.5.1.49 REG39_VAC2_ADC Register (Offset = 39h) [reset = 0h]
          1. Table 58. REG39_VAC2_ADC Register Field Descriptions
        50. 8.5.1.50 REG3B_VBAT_ADC Register (Offset = 3Bh) [reset = 0h]
          1. Table 59. REG3B_VBAT_ADC Register Field Descriptions
        51. 8.5.1.51 REG3D_VSYS_ADC Register (Offset = 3Dh) [reset = 0h]
          1. Table 60. REG3D_VSYS_ADC Register Field Descriptions
        52. 8.5.1.52 REG3F_TS_ADC Register (Offset = 3Fh) [reset = 0h]
          1. Table 61. REG3F_TS_ADC Register Field Descriptions
        53. 8.5.1.53 REG41_TDIE_ADC Register (Offset = 41h) [reset = 0h]
          1. Table 62. REG41_TDIE_ADC Register Field Descriptions
        54. 8.5.1.54 REG43_D+_ADC Register (Offset = 43h) [reset = 0h]
          1. Table 63. REG43_D+_ADC Register Field Descriptions
        55. 8.5.1.55 REG45_D-_ADC Register (Offset = 45h) [reset = 0h]
          1. Table 64. REG45_D-_ADC Register Field Descriptions
        56. 8.5.1.56 REG47_DPDM_Driver Register (Offset = 47h) [reset = 0h]
          1. Table 65. REG47_DPDM_Driver Register Field Descriptions
        57. 8.5.1.57 REG48_Part_Information Register (Offset = 48h) [reset = 0h]
          1. Table 66. REG48_Part_Information Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
        1. 12.1.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT_ON Quiescent battery current (BATP, BAT, SYS) when the charger is in the battery only mode, battery FET is enabled, ADC is disabled VBAT = 8V, No VBUS, BATFET is enabled, I2C enabled, ADC disabled, system is powered by battery. 21 24 µA
IQ_BAT_OFF Quiescent battery current (BATP) when the charger is in ship mode. VBAT = 8V, No VBUS, I2C enabled, ADC disabled, in ship mode. 12 16 µA
ISD_BAT Shutdown battery current (BATP) when charger is in shut down mode. VBAT = 8V, No VBUS, I2C disabled, ADC disabled, in shut down mode. 0.6 0.7 µA
IQ_VBUS Quiescent input current (VBUS) VBUS = 15V, VBAT = 8V, charge disabled, converter switching, ISYS = 0A, OOA disabled 3 mA
VBUS = 15V, VBAT = 8V, charge disabled, converter switching, ISYS = 0A, OOA enabled 5 mA
ISD_VBUS Shutdown input current (VBUS) in HIZ VBUS = 5V, HIZ mode, no battery, ADC disabled, ACDRV disabled 354 µA
IQ_OTG Quiescent battery current (BATP, BAT, SYS) in OTG VBAT = 8V, VBUS = 5V, OTG mode enabled, converter switching, IVBUS = 0A, OOA disabled 3 mA
VBAT = 8V, VBUS = 5V, OTG mode enabled, converter switching, IVBUS = 0A, OOA enabled 5 mA
VBUS / VBAT SUPPLY
VVAC_PRESENT VAC present rising threshold to turnon the ACFET-RBFET For both VAC1 and VAC2 3.4 3.5 V
VAC present falling threshold to turnoff the ACFET-RBFET 3.1 3.2 V
VVAC_OVP VAC overvoltage rising threshold, when VAC_OVP[1:0]=00 For both VAC1 and VAC2 25.2 26 26.8 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=00 24.4 25.2 26.0 V
VAC overvoltage rising threshold, when VAC_OVP[1:0]=01 21.1 21.7 22.3 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=01 20.6 21.2 21.8 V
VAC overvoltage rising threshold, when VAC_OVP[1:0]=10 11.6 12 12.4 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=10 11.2 11.6 12.0 V
VAC overvoltage rising threshold, when VAC_OVP[1:0]=11 6.7 7 7.3 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=11 6.5 6.8 7.1 V
VVBUS_OP VBUS operating range 3.6 24 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.25 3.4 3.55 V
VVBUS_UVLO VBUS falling to turnoff I2C, no battery VBUS falling 3.05 3.2 3.35 V
VVBUS_PRESENT VBUS to start switching VBUS rising 3.3 3.4 3.5 V
VVBUS_PRESENTZ VBUS to stop switching VBUS falling 3.1 3.2 3.3 V
VVBUS_OVP VBUS overvoltage rising threshold VBUS rising 25.2 25.7 26.2 V
VVBUS_OVPZ VBUS overvoltage falling threshold VBUS falling 24.0 24.4 24.8 V
IBUS_OCP IBUS over-current rising threshold 7.0 8.0 9.0 A
IBUS_OCPZ IBUS over-current falling threshold 6.5 7.5 8.5 A
VBAT_UVLOZ BAT voltage for active I2C and turning on BATFET, no VBUS, no VAC VBAT rising, when the charger is in ship mode 3.25 3.40 3.55 V
VBAT rising, when the charger is in normal mode 2.50 2.60 2.71 V
VBAT_UVLO BAT voltage to turn off I2C and BATFET, no VBUS, no VAC VBAT falling, when the charger is in ship mode 3.05 3.20 3.31 V
VBAT falling, when the charger is in normal mode 2.30 2.40 2.50 V
VBAT_OTG BAT voltage rising threshold to enable OTG mode VBAT rising 2.7 2.8 2.9 V
VBAT_OTGZ BAT voltage falling threshold to disable OTG mode VBAT falling 2.4 2.5 2.6 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.3 3.4 3.5 V
VPOORSRC Bad adapter detection threshold hysteresis VBUS rising above VPOORSRC 150 200 250 mV
IPOORSRC Bad adapter detection current source 30 mA
POWER-PATH MANAGEMENT
VSYSMAX_REG_RNG System voltage regulation range, measured on SYS 3.2 19 V
VSYSMAX_REG_ACC System voltage regulation accuracy (when VBAT>VSYSMIN, charging disabled, PFM disabled) VBAT = 16.8V (4s default) 16.82 17.00 17.25 V
VBAT = 12.6V (3s default) 12.62 12.80 13.04 V
VBAT = 8.4V (2s default) 8.44 8.60 8.77 V
VBAT = 4.2V (1s default) 4.268 4.40 4.550 V
VSYSMIN_REG_RNG VSYSMIN regulation range, measured on SYS 2.5 16 V
VSYSMIN_REG_STEP VSYSMIN regulation step size 250 mV
VSYSMIN_REG_ACC System voltage regulation accuracy (when VBAT<VSYSMIN) 4s battery 11.9 12.2 12.5 V
3s battery 9.0 9.2 9.4 V
2s battery 7.12 7.2 7.32 V
1s battery 3.5 3.7 3.9 V
VSYS_OVP VSYS overvoltage rising threshold As a percentage of the system regulation voltage, to turnoff the converter. 105.5 110.0 112.3 %
VSYS overvoltage falling threshold As a percentage of the system regulation voltage, to re-enable the converter. 95.5 100 102 %
VSYS_SHORT VSYS short voltage falling threshold 2.1 2.2 2.3 V
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3 18.8 V
VREG_STEP Typical charge voltage step 10 mV
VREG_ACC Charge voltage accuracy, TJ = –40°C - 85°C VREG = 16.8V -0.8 0.4 %
VREG = 12.6V -1.0 0.5 %
VREG = 8.4V -0.4 0.5 %
VREG = 4.2V -0.6 0.8 %
ICHG_RANGE Typical charge current regulation range 0.05 5 A
ICHG_STEP Typical charge current regulation step 10 mA
ICHG_ACC Typical boost mode PWM charge current accuracy, VBUS < VBAT, TJ = –40°C - 85°C ICHG = 2A; VBAT=8V -2 8 %
ICHG = 1A; VBAT=8V -2 8 %
ICHG = 0.5A; VBAT=8V -7.5 7.5 %
ICHG_ACC Typical buck mode PWM charge current accuracy, VBUS > VBAT, TJ = –40°C - 85°C ICHG = 4A; VBAT=8V -5.5 2.5 %
ICHG = 1A; VBAT=8V -5 5 %
ICHG = 0.5A; VBAT=8V -7.5 7.5 %
IPRECHG_RANGE Typical pre-charge current range 40 2000 mA
IPRECHG_STEP Typical pre-charge current step 40 mA
IPRECHG_ACC Typical LDO mode charge current accuracy when VBATP-VBATN below VSYSMIN, VBUS < VBAT, TJ = –40°C - 85°C IPRECHG = 480mA, VBAT = 6.5V -8 8 %
IPRECHG = 200mA, VBAT = 6.5V -20 20 %
IPRECHG = 120mA, VBAT = 6.5V -35 35 %
IPRECHG_ACC Typical LDO mode charge current accuracy when VBATP-VBATN below VSYSMIN, VBUS > VBAT, TJ = –40°C - 85°C IPRECHG = 1000mA, VBAT = 6.5V -4.5 3.5 %
IPRECHG = 200mA, VBAT = 6.5V -20 20 %
IPRECHG = 120mA, VBAT = 6.5V -30 30 %
IBAT_ACC IBAT pin current sensing accuracy with 25µA/A gain. The accuracy is applied to forward charging mode for charging current sensing, TJ = –40°C - 85°C IBAT = 4A, VBAT = 8V -5 5 %
IBAT = 1A, VBAT = 8V -10 10 %
IBAT = 0.5A, VBAT = 8V -20 20 %
ITERM_RANGE Typical termination current range 40 1000 mA
ITERM_STEP Typical termination current step 40 mA
ITERM_ACC Termination current accuracy, TJ = –40°C - 85°C ITERM = 120mA -20 20 %
ITERM = 480mA -14 14 %
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.25 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling 2.06 V
IBAT_SHORT Battery trickle charging current VBAT < VBAT_SHORTZ 100 mA
VBAT_LOWV_RISE Battery voltage rising threshold to start fast-charge, as percentage of VREG VBAT_LOWV=15%VREG, VBAT_LOWV_1:0=00 13 15 17 %
VBAT_LOWV=62.2%VREG, VBAT_LOWV_1:0=01 61.5 63.0 64.5 %
VBAT_LOWV=66.7%VREG, VBAT_LOWV_1:0=10 67.0 68.0 69.0 %
VBAT_LOWV=71.4%VREG, VBAT_LOWV_1:0=11 71.0 72.5 74.0 %
VBAT_LOWV_HYS Battery voltage threshold to stop fast-charge hysteresis VBAT falling, as percentage of VREG, VBAT_LOWV_1:0=11 1.4 %
VRECHG Battery recharge threshold VBAT falling, VRECHG=0011, VREG=8.4V 200 mV
VBAT falling, VRECHG=0111, VREG=16.8V 400 mV
BATFET
RBATFET MOSFET on resistance from SYS to BAT Tj = -40°C-85°C 8 9.69
BATTERY PROTECTIONS
VBAT_OVP Battery over-voltage threshold, when battery connected. VBAT rising, as percentage of VREG 103 104 105 %
VBAT falling, as percentage of VREG 101 102 103 %
VBAT_SHORT Battery short voltage VBAT falling, to clamp the charging current as trickle charging current. 2.06 V
VBAT rising, to release the trickle charging current clamp 2.25 V
IBAT_OCP Battery discharging over-current rising threshold 9.3 11.4 A
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range 3.6 22 V
VINDPM_STEP Typical input voltage regulation step 100 mV
VINDPM_ACC Input voltage regulation accuracy VINDPM=18.6V -2 2 %
VINDPM=10.6V -3 3 %
VINDPM=4.3V -5 5 %
IINDPM_RANGE Typical input current regulation range 0.1 3.3 A
IINDPM_STEP Typical input current regulation step 10 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA, VBUS=9V 415 460 500 mA
IINDPM = 1000mA, VBUS=9V 880 940 1000 mA
IINDPM = 2000mA, VBUS=9V 1800 1880 1960 mA
IINDPM = 3000mA, VBUS=9V 2720 2820 2920 mA
VILIM_REG_RNG Voltage range for input current regultion at ILIM_HIZ pin 1 4 V
ILEAK_ILIM ILIM_HIZ pin leakage current VILIM_HIZ = 4V -1.5 1.5 µA
D+ / D- DETECTION
VD+ _600MVSRC D+ voltage source (600 mV) 500 600 700 mV
ID+_10UASRC D+ current source (10 µA) VD+ = 200 mV, 7 10 14 µA
ID+_100UASNK D+ current sink (100 µA) VD+ = 500 mV, 50 90 150 µA
VD+_0P325 D+ comparator threshold for Secondary Detection D+ pin rising 250 400 mV
VD+_0P8 D+ comparator threshold for Data Contact Detection D+ pin rising 775 850 925 mV
ID+_LKG Leakage current into D+ D+ pin is in HiZ mode -1 1 µA
VD-_600MVSRC D- voltage source (600 mV) 500 600 700 mV
ID-_100UASNK D- current sink (100 µA) VD- = 500 mV, 50 90 150 µA
VD-_0P325 D- comparator threshold for Primary Detection D- pin rising 250 400 mV
ID-_LKG Leakage current into D- HiZ mode -1 1 µA
VD+ _2p8 D+ comparator threshold for non-standard adapter (combined VD+_2p8_hi and VD+_2p8_lo) 2.55 2.85 V
VD- _2p8 D- comparator threshold for non-standard adapter (combined VD-_2p8_hi and VD-_2p8_lo) 2.55 2.85 V
VD+ _2p0 D+ comparator threshold for non-standard adapter (combined VD+_2p0_hi and VD+_2p0_lo) 1.85 2.15 V
VD- _2p0 D- comparator threshold for non-standard adapter (combined VD-_2p0_hi and VD-_2p0_lo) 1.85 2.15 V
VD+ _1p2 D+ comparator threshold for non-standard adapter (combined VD+_1p2_hi and VD+_1p2_lo) 1.05 1.35 V
VD- _1p2 D- comparator threshold for non-standard adapter (combined VD-_1p2_hi and VD-_1p2_lo) 1.05 1.35 V
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 120°C 120 °C
TREG = 100°C 100 °C
TREG = 80°C 80 °C
TREG = 60°C 60 °C
TSHUT Thermal Shutdown Rising Threshold Temperature Increasing (TSHUT[1:0]=00) 130 150 170 °C
Temperature Increasing (TSHUT[1:0]=01) 110 130 150 °C
Temperature Increasing (TSHUT[1:0]=10) 100 120 140 °C
Temperature Increasing (TSHUT[1:0]=11) 65 85 105 °C
TSHUT_HYS Thermal Shutdown Falling Hysteresis Temperature Decreasing by TSHUT_HYS 30 °C
JEITA THERMISTOR COMPARATOR (CHARGE MODE)
VT1_RISE T1 comparator rising threshold, charge suspended above this voltage. As Percentage to VREGN (0°C w/ 103AT) 72.4 73.3 74.2 %
VT1_FALL T1 comparator falling threshold. charge re-enabled below this voltage. As Percentage to VREGN (3°C w/ 103AT) 71.5 72 72.5 %
VT2_RISE T2 comparator rising threshold. As Percentage to VREGN, JEITA_T2=5°C w/ 103AT 70.6 71.1 71.6 %
As Percentage to VREGN, JEITA_T2=10°C w/ 103AT 67.9 68.4 68.9 %
As Percentage to VREGN, JEITA_T2=15°C w/ 103AT 65.0 65.5 66.0 %
As Percentage to VREGN, JEITA_T2=20°C w/ 103AT 61.9 62.4 62.9 %
VT2_FALL T2 comparator falling threshold. As Percentage to VREGN, JEITA_T2=5°C w/ 103AT 69.3 69.8 70.3 %
As Percentage to VREGN, JEITA_T2=10°C w/ 103AT 66.6 67.1 67.6 %
As Percentage to VREGN, JEITA_T2=15°C w/ 103AT 63.7 64.2 64.7 %
As Percentage to VREGN, JEITA_T2=20°C w/ 103AT 60.6 61.1 61.6 %
VT3_RISE T3 comparator rising threshold. As Percentage to VREGN, JEITA_T3=40°C w/ 103AT 49.2 49.7 50.2 %
As Percentage to VREGN, JEITA_T3=45°C w/ 103AT 45.6 46.1 46.6 %
As Percentage to VREGN, JEITA_T3=50°C w/ 103AT 42.0 42.5 43.0 %
As Percentage to VREGN, JEITA_T3=55°C w/ 103AT 38.5 39 39.5 %
VT3_FALL T3 comparator falling threshold. As Percentage to VREGN, JEITA_T3=40°C w/ 103AT 47.9 48.4 48.9 %
As Percentage to VREGN, JEITA_T3=45°C w/ 103AT 44.3 44.8 45.3 %
As Percentage to VREGN, JEITA_T3=50°C w/ 103AT 40.7 41.2 41.7 %
As Percentage to VREGN, JEITA_T3=55°C w/ 103AT 37.2 37.7 38.2 %
VT5_FALL T5 comparator falling threshold, charge suspended below this voltage. As Percentage to VREGN (60°C w/ 103AT) 33.7 34.2 34.7 %
VT5_RISE T5 comparator rising threshold. charge is re-enabled above this voltage. As Percentage to VREGN (58°C w/ 103AT) 35 35.5 36 %
COLD / HOT THERMISTOR COMPARATOR (OTG MODE)
VBCOLD_RISE TCOLD comparator rising threshold. As Percentage to VREGN (–20°C w/ 103AT) 79.5 80.0 80.5 %
As Percentage to VREGN (–10°C w/ 103AT) 76.6 77.1 77.6 %
VBCOLD_FALL TCOLD comparator falling threshold. As Percentage to VREGN (–20°C w/ 103AT) 78.2 78.7 79.2 %
As Percentage to VREGN (–10°C w/ 103AT) 75.3 75.8 76.3 %
VBHOT_FALL THOT comparator falling threshold. As Percentage to VREGN, (55°C w/ 103AT) 37.2 37.7 38.2 %
As Percentage to VREGN, (60°C w/ 103AT) 33.9 34.4 34.9 %
As Percentage to VREGN, (65°C w/ 103AT) 30.8 31.3 31.8 %
VBHOT_RISE THOT comparator rising threshold. As Percentage to VREGN, (55°C w/ 103AT) 38.8 39.3 39.8 %
As Percentage to VREGN, (60°C w/ 103AT) 35.2 35.7 36.2 %
As Percentage to VREGN, (65°C w/ 103AT) 32.0 32.5 33.0 %
SWITCHING CONVERTER
FSW PWM switching frequency 1.3 1.5 1.7 MHz
650 750 850 kHz
SENSE RESISTANCE and MOSFET Rdson
RSNS VBUS to PMID input sensing resistance Tj = -40°C-85°C 6
RQ1_ON Buck high-side switching MOSFET turnon resistance between PMID and SW1 Tj = -40°C-85°C 20
RQ2_ON Buck low-side switching MOSFET turnon resistance between SW1 and PGND Tj = -40°C-85°C 30
RQ3_ON Boost low-side switching MOSFET turnon resistance between SW2 and PGND Tj = -40°C-85°C 22
RQ4_ON Boost high-side switching MOSFET turnon resistance between SW2 and SYS Tj = -40°C-85°C 13
OTG MODE CONVERTER
VOTG_RANGE Typical OTG mode voltage regulation range 2.8 22 V
VOTG_STEP Typical OTG mode voltage regulation step 10 mV
VOTG_ACC OTG mode voltage regulation accuracy IBUS = 0A, VOTG = 5V, 12V, 20V -3 3 %
IOTG_RANGE Typical OTG mode current regulation range 0.12 3.32 A
IOTG_STEP Typical OTG mode current regulation step 40 mA
IOTG_ACC OTG mode current regulation accuracy IOTG = 3.0A -2.2 2.2 %
IOTG = 1.52A -5 3 %
IOTG = 0.52A -15 8 %
VOTG_UVP OTG mode under voltage falling threshold 2.1 2.2 2.3 V
VOTG_OVP OTG mode overvoltage rising threshold As percentage of VOTG regulation, OTG mode OOA disabled. 104 113 120 %
OTG mode overvoltage falling threshold As percentage of VOTG regulation 90 98 104 %
IOTG_BAT Battery current regulation in OTG mode IBAT_REG_1:0 = 00, VBAT=8V, VOTG=9V 2.8 3 3.2 A
IBAT_REG_1:0 = 01, VBAT=8V, VOTG=9V 3.8 4 4.2 A
IBAT_REG_1:0 = 10, VBAT=8V, VOTG=9V 4.8 5 5.3 A
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.6 4.8 5 V
VVBUS = 15V, IREGN = 20mA 4.8 5 5.2 V
IREGN REGN LDO current limit VVBUS = 5V, VREGN = 4.5V 30 mA
I2C INTERFACE (SCL, SDA)
VIH_SDA Input high threshold level, SDA Pull up rail 1.8V 1.3 V
VIL_SDA Input low threshold level Pull up rail 1.8V 0.4 V
VOL_SDA Output low threshold level Sink current = 5mA 0.4 V
IBIAS_SDA High-level leakage current Pull up rail 1.8V 1 µA
VIH_SCL Input high threshold level, SDA Pull up rail 1.8V 1.3 V
VIL_SCL Input low threshold level Pull up rail 1.8V 0.4 V
VOL_SCL Output low threshold level Sink current = 5mA 0.4 V
IBIAS_SCL High-level leakage current Pull up rail 1.8V 1 µA
LOGIC I PIN (CE, ILIM_HIZ, QON)
VIH_CE Input high threshold level, CE 1.3 V
VIL_CE Input low threshold level, CE 0.4 V
IIN_BIAS_CE High-level leakage current, CE Pull up rail 1.8V 1 µA
VIH_QON Input high threshold level, QON 1.3 V
VIL_QON Input low threshold level, QON 0.4 V
VQON Internal QON pull up QON is pulled up internally 3.2 V
RQON Internal QON pull up resistance 200
VIH_ILIM_HIZ Input high threshold level, ILIM_HIZ 1 V
VIL_ILIM_HIZ Input low threshold level, ILIM_HIZ 0.75 V
LOGIC O PIN (INT, PG, STAT)
VOL_INT Output low threshold level, INT pin Sink current = 5mA 0.4 V
IOUT_BIAS_INT High-level leakage current, INT pin Pull up rail 1.8V 1 µA
VOL_PG Output low threshold level, PG pin Sink current = 5mA 0.4 V
IOUT_BIAS_PG High-level leakage current, PG pin Pull up rail 1.8V 1 µA
VOL_STAT Output low threshold level, STAT pin Sink current = 5mA 0.4 V
IOUT_BIAS_STAT High-level leakage current, STAT pin Pull up rail 1.8V 1 µA
ADC MEASUREMENT ACCURACY AND PERFORMANCE
tADC_CONV Conversion-time, Each Measurement ADC_SAMPLE[1:0] = 00 24 ms
ADC_SAMPLE[1:0] = 01 12 ms
ADC_SAMPLE[1:0] = 10 6 ms
ADC_SAMPLE[1:0] = 11 3 ms
ADCRES Effective Resolution ADC_SAMPLE[1:0] = 00 14 15 bits
ADC_SAMPLE[1:0] = 01 13 14 bits
ADC_SAMPLE[1:0] = 10 12 13 bits
ADC_SAMPLE[1:0] = 11 10 11 bits
ADC MEASUREMENT RANGE AND LSB
IBUS_ADC ADC Bus Current Reading (both forward and OTG) Range 0 5 A
LSB 1 mA
VBUS_ADC ADC Bus Voltage Reading Range 0 30 V
LSB 1 mV
VAC_ADC ADC VAC Voltage Reading Range 0 30 V
LSB 1 mV
VBAT_ADC ADC BAT Voltage Reading Range 0 20 V
LSB 1 mV
VSYS_ADC ADC SYS Voltage Reading Range 0 24 V
LSB 1 mV
IBAT_ADC ADC BAT Current Reading Range 0 8 A
LSB 1 mA
TS_ADC ADC TS Voltage Reading Range 0 99.9 %
LSB 0.098 %
TDIE_ADC ADC Die Temperature Reading Range -40 150 °C
LSB 0.5 °C