SLUSDF9 June   2020 BQ25790

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
      1.      Device Images
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Dual-Input Power Mux
        1. 8.3.3.1 VBUS Input Only
        2. 8.3.3.2 One ACFET-RBFET
        3. 8.3.3.3 Two ACFETs-RBFETs
      4. 8.3.4  Device Power Up from Battery without Input Source
      5. 8.3.5  Device Power Up from Input Source
        1. 8.3.5.1 Power Up REGN LDO
        2. 8.3.5.2 Poor Source Qualification
        3. 8.3.5.3 Input Source Type Detection
          1. 8.3.5.3.1 D+/D– Detection Sets Input Current Limit
          2. 8.3.5.3.2 Force Input Current Limit Detection
          3. 8.3.5.3.3 Connector Fault Detection
        4. 8.3.5.4 Input Current Optimizer (ICO)
        5. 8.3.5.5 Default VINDPM Setting
        6. 8.3.5.6 Device HIZ State
        7. 8.3.5.7 ILIM_HIZ Pin
        8. 8.3.5.8 IBAT Pin for Battery Current Sensing
        9. 8.3.5.9 Buck-Boost Converter Operation
          1. 8.3.5.9.1 Pulse Frequency Modulation (PFM)
      6. 8.3.6  USB On-The-Go (OTG)
        1. 8.3.6.1 OTG Mode to Power External Devices
      7. 8.3.7  Power Path Management
        1. 8.3.7.1 Narrow VDC Architecture
        2. 8.3.7.2 Dynamic Power Management
      8. 8.3.8  Battery Charging Management
        1. 8.3.8.1 Autonomous Charging Cycle
        2. 8.3.8.2 Battery Charging Profile
        3. 8.3.8.3 Charging Termination
        4. 8.3.8.4 Charging Safety Timer
        5. 8.3.8.5 Thermistor Qualification
          1. 8.3.8.5.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.8.5.2 Cold/Hot Temperature Window in OTG Mode
      9. 8.3.9  Integrated 16-Bit ADC for Monitoring
      10. 8.3.10 Status Outputs (PG, STAT, and INT)
        1. 8.3.10.1 Power Good Indicator (PG)
        2. 8.3.10.2 Charging Status Indicator (STAT Pin)
        3. 8.3.10.3 Interrupt to Host (INT)
      11. 8.3.11 Ship FET Control
        1. 8.3.11.1 Shutdown Mode
        2. 8.3.11.2 Ship Mode
        3. 8.3.11.3 System Power Reset
      12. 8.3.12 Protections
        1. 8.3.12.1 Voltage and Current Monitoring
        2. 8.3.12.2 Thermal Regulation and Thermal Shutdown
      13. 8.3.13 Serial Interface
        1. 8.3.13.1 Data Validity
        2. 8.3.13.2 START and STOP Conditions
        3. 8.3.13.3 Byte Format
        4. 8.3.13.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.13.5 Slave Address and Data Direction Bit
        6. 8.3.13.6 Single Write and Read
        7. 8.3.13.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
        1. 8.5.1.1  REG00_Minimal_System_Voltage Register (Offset = 0h) [reset = X]
          1. Table 10. REG00_Minimal_System_Voltage Register Field Descriptions
        2. 8.5.1.2  REG01_Charge_Voltage_Limit Register (Offset = 1h) [reset = X]
          1. Table 11. REG01_Charge_Voltage_Limit Register Field Descriptions
        3. 8.5.1.3  REG03_Charge_Current_Limit Register (Offset = 3h) [reset = X]
          1. Table 12. REG03_Charge_Current_Limit Register Field Descriptions
        4. 8.5.1.4  REG05_Input_Voltage_Limit Register (Offset = 5h) [reset = 24h]
          1. Table 13. REG05_Input_Voltage_Limit Register Field Descriptions
        5. 8.5.1.5  REG06_Input_Current_Limit Register (Offset = 6h) [reset = 12Ch]
          1. Table 14. REG06_Input_Current_Limit Register Field Descriptions
        6. 8.5.1.6  REG08_Precharge_Control Register (Offset = 8h) [reset = C3h]
          1. Table 15. REG08_Precharge_Control Register Field Descriptions
        7. 8.5.1.7  REG09_Termination_Control Register (Offset = 9h) [reset = 5h]
          1. Table 16. REG09_Termination_Control Register Field Descriptions
        8. 8.5.1.8  REG0A_Re-charge_Control Register (Offset = Ah) [reset = X]
          1. Table 17. REG0A_Re-charge_Control Register Field Descriptions
        9. 8.5.1.9  REG0B_VOTG_regulation Register (Offset = Bh) [reset = DCh]
          1. Table 18. REG0B_VOTG_regulation Register Field Descriptions
        10. 8.5.1.10 REG0D_IOTG_regulation Register (Offset = Dh) [reset = 4Bh]
          1. Table 19. REG0D_IOTG_regulation Register Field Descriptions
        11. 8.5.1.11 REG0E_Timer_Control Register (Offset = Eh) [reset = 3Dh]
          1. Table 20. REG0E_Timer_Control Register Field Descriptions
        12. 8.5.1.12 REG0F_Charger_Control_0 Register (Offset = Fh) [reset = A2h]
          1. Table 21. REG0F_Charger_Control_0 Register Field Descriptions
        13. 8.5.1.13 REG10_Charger_Control_1 Register (Offset = 10h) [reset = 85h]
          1. Table 22. REG10_Charger_Control_1 Register Field Descriptions
        14. 8.5.1.14 REG11_Charger_Control_2 Register (Offset = 11h) [reset = 40h]
          1. Table 23. REG11_Charger_Control_2 Register Field Descriptions
        15. 8.5.1.15 REG12_Charger_Control_3 Register (Offset = 12h) [reset = 0h]
          1. Table 24. REG12_Charger_Control_3 Register Field Descriptions
        16. 8.5.1.16 REG13_Charger_Control_4 Register (Offset = 13h) [reset = X]
          1. Table 25. REG13_Charger_Control_4 Register Field Descriptions
        17. 8.5.1.17 REG14_Charger_Control_5 Register (Offset = 14h) [reset = 16h]
          1. Table 26. REG14_Charger_Control_5 Register Field Descriptions
        18. 8.5.1.18 REG15_Reserved Register (Offset = 15h) [reset = 00h]
          1. Table 27. REG15_Reserved Register Field Descriptions
        19. 8.5.1.19 REG16_Temperature_Control Register (Offset = 16h) [reset = C0h]
          1. Table 28. REG16_Temperature_Control Register Field Descriptions
        20. 8.5.1.20 REG17_NTC_Control_0 Register (Offset = 17h) [reset = 7Ah]
          1. Table 29. REG17_NTC_Control_0 Register Field Descriptions
        21. 8.5.1.21 REG18_NTC_Control_1 Register (Offset = 18h) [reset = 54h]
          1. Table 30. REG18_NTC_Control_1 Register Field Descriptions
        22. 8.5.1.22 REG19_ICO_Current_Limit Register (Offset = 19h) [reset = 0h]
          1. Table 31. REG19_ICO_Current_Limit Register Field Descriptions
        23. 8.5.1.23 REG1B_Charger_Status_0 Register (Offset = 1Bh) [reset = 0h]
          1. Table 32. REG1B_Charger_Status_0 Register Field Descriptions
        24. 8.5.1.24 REG1C_Charger_Status_1 Register (Offset = 1Ch) [reset = 0h]
          1. Table 33. REG1C_Charger_Status_1 Register Field Descriptions
        25. 8.5.1.25 REG1D_Charger_Status_2 Register (Offset = 1Dh) [reset = 0h]
          1. Table 34. REG1D_Charger_Status_2 Register Field Descriptions
        26. 8.5.1.26 REG1E_Charger_Status_3 Register (Offset = 1Eh) [reset = 0h]
          1. Table 35. REG1E_Charger_Status_3 Register Field Descriptions
        27. 8.5.1.27 REG1F_Charger_Status_4 Register (Offset = 1Fh) [reset = 0h]
          1. Table 36. REG1F_Charger_Status_4 Register Field Descriptions
        28. 8.5.1.28 REG20_FAULT_Status_0 Register (Offset = 20h) [reset = 0h]
          1. Table 37. REG20_FAULT_Status_0 Register Field Descriptions
        29. 8.5.1.29 REG21_FAULT_Status_1 Register (Offset = 21h) [reset = 0h]
          1. Table 38. REG21_FAULT_Status_1 Register Field Descriptions
        30. 8.5.1.30 REG22_Charger_Flag_0 Register (Offset = 22h) [reset = 0h]
          1. Table 39. REG22_Charger_Flag_0 Register Field Descriptions
        31. 8.5.1.31 REG23_Charger_Flag_1 Register (Offset = 23h) [reset = 0h]
          1. Table 40. REG23_Charger_Flag_1 Register Field Descriptions
        32. 8.5.1.32 REG24_Charger_Flag_2 Register (Offset = 24h) [reset = 0h]
          1. Table 41. REG24_Charger_Flag_2 Register Field Descriptions
        33. 8.5.1.33 REG25_Charger_Flag_3 Register (Offset = 25h) [reset = 0h]
          1. Table 42. REG25_Charger_Flag_3 Register Field Descriptions
        34. 8.5.1.34 REG26_FAULT_Flag_0 Register (Offset = 26h) [reset = 0h]
          1. Table 43. REG26_FAULT_Flag_0 Register Field Descriptions
        35. 8.5.1.35 REG27_FAULT_Flag_1 Register (Offset = 27h) [reset = 0h]
          1. Table 44. REG27_FAULT_Flag_1 Register Field Descriptions
        36. 8.5.1.36 REG28_Charger_Mask_0 Register (Offset = 28h) [reset = 0h]
          1. Table 45. REG28_Charger_Mask_0 Register Field Descriptions
        37. 8.5.1.37 REG29_Charger_Mask_1 Register (Offset = 29h) [reset = 0h]
          1. Table 46. REG29_Charger_Mask_1 Register Field Descriptions
        38. 8.5.1.38 REG2A_Charger_Mask_2 Register (Offset = 2Ah) [reset = 0h]
          1. Table 47. REG2A_Charger_Mask_2 Register Field Descriptions
        39. 8.5.1.39 REG2B_Charger_Mask_3 Register (Offset = 2Bh) [reset = 0h]
          1. Table 48. REG2B_Charger_Mask_3 Register Field Descriptions
        40. 8.5.1.40 REG2C_FAULT_Mask_0 Register (Offset = 2Ch) [reset = 0h]
          1. Table 49. REG2C_FAULT_Mask_0 Register Field Descriptions
        41. 8.5.1.41 REG2D_FAULT_Mask_1 Register (Offset = 2Dh) [reset = 0h]
          1. Table 50. REG2D_FAULT_Mask_1 Register Field Descriptions
        42. 8.5.1.42 REG2E_ADC_Control Register (Offset = 2Eh) [reset = 30h]
          1. Table 51. REG2E_ADC_Control Register Field Descriptions
        43. 8.5.1.43 REG2F_ADC_Function_Disable_0 Register (Offset = 2Fh) [reset = 0h]
          1. Table 52. REG2F_ADC_Function_Disable_0 Register Field Descriptions
        44. 8.5.1.44 REG30_ADC_Function_Disable_1 Register (Offset = 30h) [reset = 0h]
          1. Table 53. REG30_ADC_Function_Disable_1 Register Field Descriptions
        45. 8.5.1.45 REG31_IBUS_ADC Register (Offset = 31h) [reset = 0h]
          1. Table 54. REG31_IBUS_ADC Register Field Descriptions
        46. 8.5.1.46 REG33_IBAT_ADC Register (Offset = 33h) [reset = 0h]
          1. Table 55. REG33_IBAT_ADC Register Field Descriptions
        47. 8.5.1.47 REG35_VBUS_ADC Register (Offset = 35h) [reset = 0h]
          1. Table 56. REG35_VBUS_ADC Register Field Descriptions
        48. 8.5.1.48 REG37_VAC1_ADC Register (Offset = 37h) [reset = 0h]
          1. Table 57. REG37_VAC1_ADC Register Field Descriptions
        49. 8.5.1.49 REG39_VAC2_ADC Register (Offset = 39h) [reset = 0h]
          1. Table 58. REG39_VAC2_ADC Register Field Descriptions
        50. 8.5.1.50 REG3B_VBAT_ADC Register (Offset = 3Bh) [reset = 0h]
          1. Table 59. REG3B_VBAT_ADC Register Field Descriptions
        51. 8.5.1.51 REG3D_VSYS_ADC Register (Offset = 3Dh) [reset = 0h]
          1. Table 60. REG3D_VSYS_ADC Register Field Descriptions
        52. 8.5.1.52 REG3F_TS_ADC Register (Offset = 3Fh) [reset = 0h]
          1. Table 61. REG3F_TS_ADC Register Field Descriptions
        53. 8.5.1.53 REG41_TDIE_ADC Register (Offset = 41h) [reset = 0h]
          1. Table 62. REG41_TDIE_ADC Register Field Descriptions
        54. 8.5.1.54 REG43_D+_ADC Register (Offset = 43h) [reset = 0h]
          1. Table 63. REG43_D+_ADC Register Field Descriptions
        55. 8.5.1.55 REG45_D-_ADC Register (Offset = 45h) [reset = 0h]
          1. Table 64. REG45_D-_ADC Register Field Descriptions
        56. 8.5.1.56 REG47_DPDM_Driver Register (Offset = 47h) [reset = 0h]
          1. Table 65. REG47_DPDM_Driver Register Field Descriptions
        57. 8.5.1.57 REG48_Part_Information Register (Offset = 48h) [reset = 0h]
          1. Table 66. REG48_Part_Information Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
        1. 12.1.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

JEITA Guideline Compliance in Charge Mode

To improve the safety of charging Li-ion batteries, the JEITA guideline was released on April 20, 2007. The guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges.

To initiate a charge cycle, the voltage on the TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the VT1-VT5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5 range. At cool temperature T1-T2, JEITA recommends to reduce the charge current to be lower than half of the charge current at normal temperature T2-T3. The charger register bits JEITA_ISETC[1:0] provide the charge current programmability at T1-T2, to be 20%, 40% or 100% of the charge current in the T2-T3 temperature range or charge suspend. At warm temperature T3-T5, JEITA recommends charge voltage less than 4.1V / cell. The charger register bits JEITA_VSET[2:0] provide the charge voltage programmability at T3-T5, to be with a voltage offset less than charge voltage in the T2-T3 temperature range or charge suspend.

Charging termination is still enabled (when EN_TERM = 1) at cool temperature T1-T2 and warm temperature T3-T5. The termination current remains the same in all different temperature ranges. In normal operation, battery charging terminates when the charge current is lower than the termination current, the battery voltage is higher than the battery recharge voltage and the charger is in the battery voltage CV regulation loop. When the temperature enters the T1-T2 or T3-T5 ranges, the charge current may reduce to 20% or 40% of that in the T2-T3 range, which might be lower than the termination current setting. If at this moment, the battery voltage is already higher than the battery recharge voltage and the charger is in the battery voltage CV regulation loop, the charger terminates charge.

In warm T3-T5 temperature range, the battery voltage regulation value become lower than that in the T2-T3 temperature range. If the battery voltage is already very close to the T2-T3 regulation value, the JEITA warm automatic regulation voltage reduction might cause a battery over-voltage (VBAT_OVP) fault.

In cool T1-T2 temperature range or warm T3-T5 temperature range, the charge current is different from that at the normal T2-T3 temperature range , the safety timer must be adjusted accordingly. The safety timer is suspended when the charge is suspended, and runs at half of the clock rate when the charge current is reduced to 20% or 40%, but stays the same when the charge current is unchanged.

One typical JEITA charging values are shown as the figure below, in which the blue real line is the default setting and the red dash line is the programmable options.

BQ25790 slvse40_charging_Values.gifFigure 24. TS Charging Values

The NTC monitoring on the battery temperature can be ignored by the charger if TS_IGNORE = 1. When the TS pin feedback is ignored, the charger considers the TS is always good for charging and OTG modes. The TS_STAT including TS_COLD_STAT, TS_COOL_STAT, TS_WARM_STAT and TS_HOT_STAT, always report 000 with TS_IGNORE = 1.

When TS_IGNORE = 0, the charger adjusts the charging profile based on the TS pin feedback information. When the battery temperature jumps from one temperature range to the other one, the associated TS status bits are updated accordingly. The TS flag bits are set for the temperature range for which the TS voltage is reporting, and an INT pulse is asserted to alert the host if TS_MASK is low. The FLAG and INT pulse can be individually masked by properly setting the associated mask bit, to prevent the INT pulse from alerting the host of battery temperature range changes.

The typical TS resistor network is illustrated in the figure below.

BQ25790 slvse40_ts_resistor_network.gifFigure 25. TS Resistor Network

Assuming a 103AT NTC thermistor on the battery pack as shown above, the value of TSR1 and TSR2 can be determined by:

Equation 1. BQ25790 JEITA_EQ1.gif
Equation 2. BQ25790 JEITA_EQ2.gif

The BQ25790 provides the comparators with fixed thresholds for VT1 and VT5, and the comparators with programmable thresholds for VT2 and VT3. The thresholds for VT2 and VT3 are controlled by TS_COOL[1:0] and TS_WARM[1:0]. This programmability gives more flexibility for the configuration of the JEITA profile. Select T1=0°C and T5=60°C for Li-ion or Li-polymer battery, the RT1 and RT2 are calculated to be 5.24KΩ and 30.31KΩ respectively.