SLUSDV2A May   2020  ā€“ May 2021 BQ25798

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Device Power Up from Battery without Input Source
      4. 8.3.4  Device Power Up from Input Source
        1. 8.3.4.1 Power Up REGN LDO
        2. 8.3.4.2 Poor Source Qualification
        3. 8.3.4.3 ILIM_HIZ Pin
        4. 8.3.4.4 Default VINDPM Setting
        5. 8.3.4.5 Input Source Type Detection
          1. 8.3.4.5.1 D+/Dā€“ Detection Sets Input Current Limit
          2. 8.3.4.5.2 HVDCP Detection Procedure
          3. 8.3.4.5.3 Connector Fault Detection
      5. 8.3.5  Dual-Input Power Mux
        1. 8.3.5.1 ACDRV Turn On Condition
        2. 8.3.5.2 VBUS Input Only
        3. 8.3.5.3 One ACFET-RBFET
        4. 8.3.5.4 Two ACFETs-RBFETs
      6. 8.3.6  Buck-Boost Converter Operation
        1. 8.3.6.1 Force Input Current Limit Detection
        2. 8.3.6.2 Input Current Optimizer (ICO)
        3. 8.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 8.3.6.4 Pulse Frequency Modulation (PFM)
        5. 8.3.6.5 Device HIZ State
      7. 8.3.7  USB On-The-Go (OTG)
        1. 8.3.7.1 OTG Mode to Power External Devices
        2. 8.3.7.2 Backup Power Supply Mode
        3. 8.3.7.3 Backup Mode with Dual Input Mux
      8. 8.3.8  Power Path Management
        1. 8.3.8.1 Narrow VDC Architecture
        2. 8.3.8.2 Dynamic Power Management
      9. 8.3.9  Battery Charging Management
        1. 8.3.9.1 Autonomous Charging Cycle
        2. 8.3.9.2 Battery Charging Profile
        3. 8.3.9.3 Charging Termination
        4. 8.3.9.4 Charging Safety Timer
        5. 8.3.9.5 Thermistor Qualification
          1. 8.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 8.3.10 Integrated 16-Bit ADC for Monitoring
      11. 8.3.11 Status Outputs ( STAT, and INT)
        1. 8.3.11.1 Charging Status Indicator (STAT Pin)
        2. 8.3.11.2 Interrupt to Host ( INT)
      12. 8.3.12 Ship FET Control
        1. 8.3.12.1 Shutdown Mode
        2. 8.3.12.2 Ship Mode
        3. 8.3.12.3 System Power Reset
      13. 8.3.13 Protections
        1. 8.3.13.1 Voltage and Current Monitoring
          1. 8.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 8.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 8.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 8.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 8.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 8.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 8.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 8.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 8.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 8.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 8.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 8.3.14 Serial Interface
        1. 8.3.14.1 Data Validity
        2. 8.3.14.2 START and STOP Conditions
        3. 8.3.14.3 Byte Format
        4. 8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.14.5 Slave Address and Data Direction Bit
        6. 8.3.14.6 Single Write and Read
        7. 8.3.14.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PV Panel Selection
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input (VBUS / PMID) Capacitor
        4. 9.2.2.4 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VBUS Input Only

In this configuration, only a single input is connected to VBUS, so that no power MOSFETs are required. VAC1 and VAC2 are shorted to VBUS, and ACDRV1 and ACDRV2 are pulled down to GND, as shown in Figure 8-2. At POR, the charger detects that no ACFETs or RBFETs are present by sensing that the ACDRV1 and ACDRV2 pins are both shorted to GND and configures power mux register fields as shown in Table 8-5.

GUID-24C431FC-534A-47D8-9273-AAA6AEAE0829-low.gif Figure 8-2 Single Input Connected to VBUS Directly Without ACFET-RBFET
Table 8-5 Single Input Configuration Summary
PIN OR REGISTER FIELD STATE
External MOSFETs No external power mux MOSFETs.
VAC1 pin Shorted to VBUS
VAC2 pin Shorted to VBUS
ACDRV1 pin Shorted to GND
ACDRV2 pin Shorted to GND
ACRB1_STAT 0 (Read Only)
ACRB2_STAT 0 (Read Only)
DIS_ACDRV 1
EN_ACDRV1 Locked at 0
EN_ACDRV2 Locked at 0