SLUSDV2A May   2020  – May 2021 BQ25798

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Device Power Up from Battery without Input Source
      4. 8.3.4  Device Power Up from Input Source
        1. 8.3.4.1 Power Up REGN LDO
        2. 8.3.4.2 Poor Source Qualification
        3. 8.3.4.3 ILIM_HIZ Pin
        4. 8.3.4.4 Default VINDPM Setting
        5. 8.3.4.5 Input Source Type Detection
          1. 8.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 8.3.4.5.2 HVDCP Detection Procedure
          3. 8.3.4.5.3 Connector Fault Detection
      5. 8.3.5  Dual-Input Power Mux
        1. 8.3.5.1 ACDRV Turn On Condition
        2. 8.3.5.2 VBUS Input Only
        3. 8.3.5.3 One ACFET-RBFET
        4. 8.3.5.4 Two ACFETs-RBFETs
      6. 8.3.6  Buck-Boost Converter Operation
        1. 8.3.6.1 Force Input Current Limit Detection
        2. 8.3.6.2 Input Current Optimizer (ICO)
        3. 8.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 8.3.6.4 Pulse Frequency Modulation (PFM)
        5. 8.3.6.5 Device HIZ State
      7. 8.3.7  USB On-The-Go (OTG)
        1. 8.3.7.1 OTG Mode to Power External Devices
        2. 8.3.7.2 Backup Power Supply Mode
        3. 8.3.7.3 Backup Mode with Dual Input Mux
      8. 8.3.8  Power Path Management
        1. 8.3.8.1 Narrow VDC Architecture
        2. 8.3.8.2 Dynamic Power Management
      9. 8.3.9  Battery Charging Management
        1. 8.3.9.1 Autonomous Charging Cycle
        2. 8.3.9.2 Battery Charging Profile
        3. 8.3.9.3 Charging Termination
        4. 8.3.9.4 Charging Safety Timer
        5. 8.3.9.5 Thermistor Qualification
          1. 8.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 8.3.10 Integrated 16-Bit ADC for Monitoring
      11. 8.3.11 Status Outputs ( STAT, and INT)
        1. 8.3.11.1 Charging Status Indicator (STAT Pin)
        2. 8.3.11.2 Interrupt to Host ( INT)
      12. 8.3.12 Ship FET Control
        1. 8.3.12.1 Shutdown Mode
        2. 8.3.12.2 Ship Mode
        3. 8.3.12.3 System Power Reset
      13. 8.3.13 Protections
        1. 8.3.13.1 Voltage and Current Monitoring
          1. 8.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 8.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 8.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 8.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 8.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 8.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 8.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 8.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 8.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 8.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 8.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 8.3.14 Serial Interface
        1. 8.3.14.1 Data Validity
        2. 8.3.14.2 START and STOP Conditions
        3. 8.3.14.3 Byte Format
        4. 8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.14.5 Slave Address and Data Direction Bit
        6. 8.3.14.6 Single Write and Read
        7. 8.3.14.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PV Panel Selection
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input (VBUS / PMID) Capacitor
        4. 9.2.2.4 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Backup Power Supply Mode

By utilizing the charger bidirectional buck-boost operation, BQ25798 supports the backup power supply mode. In this mode, the charger discharges the energy stored in the battery or the capacitors to hold the VBUS voltage for certain amount of time after the adapter is disconnected. The backup mode only can be enabled when VBUS is high, by setting EN_BACKUP = 1. When VBUS becomes low, the charger resets EN_BACKUP bit to 0.

A comparator is monitoring the VBUS voltage. Once the adapter is disconnected, and the VBUS drops lower than the pre-set threshold, the charger terminates the forward charging mode, forces EN_OTG = 1, starts discharging the battery or supercapacitor to regulate the VBUS voltage at the VOTG register setting. After the charger enters the backup mode, the VBUS_STAT[3:0] is changed to “In the backup OTG mode” status (VBUS_STAT[3:0] = 1100). At the same time, an INT pulse is asserted and the VBUS_FLAG is set to 1, if VBUS_MASK = 0.

The comparator thresholds monitoring VBUS to trigger backup mode are programmed in the VBUS_BACKUP[1:0] register bits, as a ratio of VINDPM values. The host is not able to write EN_OTG = 1 when VBUS is high. Only when EN_BACKUP = 1 and VBUS drops lower than the threshold, the charger itself forces EN_OTG = 1 to enter the backup mode.

The ACFET1-RBFET1 is required for the backup mode operation. Once the backup mode is triggered, the charger turns off the ACFET1-REFET1 by setting DIS_ACDRV = 1, to avoid back driving the adapter in the event when the adapter is still physically connected at VAC1. The ACFET1-RBFET1 also provides the charger input over-voltage (VAC_OVP) protection. When the input voltage is higher than the programmable VAC_OVP threshold (VAC_OVP[1:0]), the charger turns off the ACFET1-RBFET1, changes from forward charging mode to backup mode. If there is no ACFET1-RBFET1 detected at POR, the charger blocks backup mode from being enabled by forcing EN_BACKUP = 0.

If the charger is running in backup mode, either of the two conditions listed below can force the charger to exit the backup operation:

  • When the battery or the capacitors voltage is discharged lower than VBAT_OTGZ
  • The host sets the EN_OTG bit from 1 to 0

If there is an adapter reconnected while the charger is in backup mode, the user may transition the source which powers the PMID load from the battery back to the adapter. The following sequence is used to switch from the battery power back to ACIN1 while simultaneously re-arming the backup mode:

  1. Write BKUP_ACFET1_ON (REG0x16[0]) register bit to 1. Setting BKUP_ACFET1 _ON = 1 will cause the device to set DIS_ACDRV = 0 and EN_ACDRV1 = 1. After that, backup mode is disabled, however, the charger remains in the normal OTG mode. The ACFET1-RBFET1 is turned on to connect the adapter to VBUS. The user must ensure the adapter voltage is equal to or higher than the charger VOTG voltage setting, otherwise, the charger OTG output might back drive the adapter connected to VBUS.
  2. Determine the source at ACIN1 is valid (is not in overvoltage and did not fail poor source detection) by reading back EN_ACDRV1 as 1.
  3. Set EN_OTG = 0, in order to exit OTG mode and enter the forward charging mode without PMID voltage crash. Setting BKUP_ACFET1_ON = 1, also clears BKUP_ACFET1_ON to 0 and sets EN_BACKUP to 1.

In a normal adapter attach sequence, the poor source detection is run, the ILIM pin is measured to set IINDPM and the VBUS is measured to set the VINDPM. In order to complete step 3 in the above sequence to re-arm the backup mode without allowing the power stage to be turned off, this sequence is skipped. This allows the converter to quickly transition back into backup mode if the adapter is unexpectedly removed during the sequence. This only occurs when EN_OTG is set to 0 while BKUP_ACFET1_ON = 1. If BKUP_ACFET1_ON = 0, or EN_OTG is already 0 when the adapter is attached, the charger powers up normally. It is generally recommended to allow 5 seconds of settling time before attempting to re-arm backup mode.

Because VBUS is not measured during the re-arming sequence, the VINDPM is not updated. In most applications, the device is expected to support a single adapter so that the previously-set VINDPM value is still accurate. For those applications where different adapter voltages are possible, the user can manually set the VINDPM value by measuring VBUS with the ADC before initiating the re-arming sequence, scaling the value and writing into the REG05_Input_Voltage_Limit Register.

In order to transition back to adapter power without dropping VBUS, but keep backup mode disarmed, the following sequence is used:

  1. Write BKUP_ACFET1_ON (REG0x16[0]) register bit to 1. Setting BKUP_ACFET1 _ON = 1 will cause the device to change EN_BACKUP = 0, DIS_ACDRV = 0 and EN_ACDRV1 = 1. After that, backup mode is disabled, however, the charger remains in the normal OTG mode. The ACFET1-RBFET1 is turned on to connect the adapter to VBUS. The user must ensure the adapter voltage is equal to or higher than the charger VOTG voltage setting, otherwise, the charger OTG output might back drive the adapter connected to VBUS.
  2. Determine the source at ACIN1 is valid (is not in overvoltage and did not fail poor source detection) by reading back EN_ACDRV1 as 1.
  3. Set BKUP_ACFET1_ON = 0
  4. Set EN_OTG = 0, in order to exit OTG mode and enter the forward charging mode without PMID voltage crash. Since BKUP_ACFET1_ON is 0, EN_BCKUP will remain at 0.

The simplified application diagram for the backup mode is shown as the figure below, in which the power flow is illustrated by the blue arrow.

GUID-61967C13-C19C-40BD-A627-08DF56A6D94D-low.gif Figure 8-6 The Simplified Application Diagram for the Backup Mode

The battery discharge current will be limited during backup mode if IBAT_REG[1:0] is set to 00, 01 or 10 (3A, 4A or 5A.) It is recommended to set IBAT_REG[1:0] = 11 (Disabled) when using backup mode in order to have optimal response. Depending on the loading at PMID, additional low ESR capacitance up to 200 μF may be necessary to prevent PMID dipping below the VINDPM set point.