SLUSDV2A May   2020  – May 2021 BQ25798


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Device Power Up from Battery without Input Source
      4. 8.3.4  Device Power Up from Input Source
        1. Power Up REGN LDO
        2. Poor Source Qualification
        3. ILIM_HIZ Pin
        4. Default VINDPM Setting
        5. Input Source Type Detection
          1. D+/D– Detection Sets Input Current Limit
          2. HVDCP Detection Procedure
          3. Connector Fault Detection
      5. 8.3.5  Dual-Input Power Mux
        1. ACDRV Turn On Condition
        2. VBUS Input Only
        3. One ACFET-RBFET
        4. Two ACFETs-RBFETs
      6. 8.3.6  Buck-Boost Converter Operation
        1. Force Input Current Limit Detection
        2. Input Current Optimizer (ICO)
        3. Maximum Power Point Tracking for Small PV Panel
        4. Pulse Frequency Modulation (PFM)
        5. Device HIZ State
      7. 8.3.7  USB On-The-Go (OTG)
        1. OTG Mode to Power External Devices
        2. Backup Power Supply Mode
        3. Backup Mode with Dual Input Mux
      8. 8.3.8  Power Path Management
        1. Narrow VDC Architecture
        2. Dynamic Power Management
      9. 8.3.9  Battery Charging Management
        1. Autonomous Charging Cycle
        2. Battery Charging Profile
        3. Charging Termination
        4. Charging Safety Timer
        5. Thermistor Qualification
          1. JEITA Guideline Compliance in Charge Mode
          2. Cold/Hot Temperature Window in OTG Mode
      10. 8.3.10 Integrated 16-Bit ADC for Monitoring
      11. 8.3.11 Status Outputs ( STAT, and INT)
        1. Charging Status Indicator (STAT Pin)
        2. Interrupt to Host ( INT)
      12. 8.3.12 Ship FET Control
        1. Shutdown Mode
        2. Ship Mode
        3. System Power Reset
      13. 8.3.13 Protections
        1. Voltage and Current Monitoring
          1.  VAC Over-voltage Protection (VAC_OVP)
          2.  VBUS Over-voltage Protection (VBUS_OVP)
          3.  VBUS Under-voltage Protection (POORSRC)
          4.  System Over-voltage Protection (VSYS_OVP)
          5.  System Short Protection (VSYS_SHORT)
          6.  Battery Over-voltage Protection (VBAT_OVP)
          7.  Battery Over-current Protection (IBAT_OCP)
          8.  Input Over-current Protection (IBUS_OCP)
          9.  OTG Over-voltage Protection (OTG_OVP)
          10. OTG Under-voltage Protection (OTG_UVP)
        2. Thermal Regulation and Thermal Shutdown
      14. 8.3.14 Serial Interface
        1. Data Validity
        2. START and STOP Conditions
        3. Byte Format
        4. Acknowledge (ACK) and Not Acknowledge (NACK)
        5. Slave Address and Data Direction Bit
        6. Single Write and Read
        7. Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. PV Panel Selection
        2. Inductor Selection
        3. Input (VBUS / PMID) Capacitor
        4. Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
JEITA Guideline Compliance in Charge Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges.

To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the VT1-VT5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5 range.

At cool temperature T1-T2, JEITA recommends to reduce the charge current to be lower than half of the charge current at normal temperature T2-T3. The device provides the programmability of the charge current at T1-T2, to be 20%, 40% or 100% of the charge current at T2-T3 or charge suspend, which is controlled by the register bits JEITA_ISETC.

The device provides the programmability of the charge voltage at T3-T5, to be with a voltage offset (0mV, 100mV or 200mV) less than charge voltage at T2-T3 or charge suspend, which is controlled by the register bits JEITA_VSET.

The charger also provides flexible voltage/current settings beyond the JEITA requirements. The charge current setting at warm temperature T3-T5 can be configured to be 20%, 40% or 100% of the charge current at T2-T3 or charge suspend, which is programmed by the register bits JEITA_ISETH.

The charge termination is still enabled (when EN_TERM=1) at cool temperature T1-T2 and warm temperature T3-T5. The termination current will be kept as the same in all different temperature ranges. In the normal operation, the charge will be terminated based on the charge current is lower than the termination current, the battery voltage is higher than the battery recharge voltage and the charger is in the battery voltage regulation loop. When the temperature enters T1-T2 or T3-T5, the charge current might drop to 20% or 40% of that at T2-T3, which might be lower than the termination current setting. If at this moment, the battery voltage is already higher than the battery recharge voltage and the charger is in the battery voltage regulation loop, the charge will be terminated.

At warm temperature T3-T5, the battery charge voltage will becomes lower. If the battery voltage is already very close to the battery charge voltage at T2-T3, to reduce the charge voltage by an offset might trigger the VBAT_OVP. The charger should response as the normal VBAT_OVP protection under this scenario.

At cool temperature T1-T2 or warm temperature T3-T5, the charge current will become different from that at the normal temperature range T2-T3, the safety timer should be adjusted accordingly. The safety timer will be suspended when the charge is suspended, and will run at half of the clock rate when the charge current is reduced to 20% or 40%, and will keep the same when the charge current is unchanged.

JEITA charging values are shown in Figure 8-11, in which the blue real line is the default setting and the red dash line is the programmable options.

GUID-FA8F0ED2-1316-40D0-BA85-76F5238193A7-low.gif Figure 8-11 TS Charging Values

The NTC monitoring on the battery temperature can be ignored by the charger if TS_IGNORE = 1. When the TS pin feedback is ignored, the charger considers the TS is always good for charging and OTG modes. The TS_STAT including TS_COLD_STAT, TS_COOL_STAT, TS_WARM_STAT and TS_HOT_STAT, always report 000 with TS_IGNORE = 1.

When TS_IGNORE = 0, the charger adjusts the charging profile based on the TS pin feedback information. When the battery temperature crosses from one temperature range to the other one, the associated TS status bits are updated accordingly. The TS flag bits are set for the temperature range for which the TS voltage is reporting, and an INT pulse is asserted to alert the host if TS_MASK is low. The FLAG and INT pulse can be individually masked by properly setting the associated mask bit, to prevent the INT pulse from alerting the host of battery temperature range changes.

The typical TS resistor network is illustrated in Figure 8-12.

GUID-A85C4C72-C36B-4F66-A290-1031A1FFC16F-low.gif Figure 8-12 TS Resistor Network

Assuming a 103AT NTC thermistor on the battery pack, the value of TSR1 and TSR2 can be determined by:

Equation 2. GUID-1D3FA77E-B9FC-4FAC-82A0-9CC1E77C078C-low.gif
Equation 3. GUID-46D9DA88-CB58-4F84-AA85-04583DB3F03F-low.gif

where VT# are the percentages of V(REGN) per the electrical spec table. The BQ25798 provides comparators with fixed thresholds for VT1 x V(REGN) and VT5 x V(REGN), and comparators with programmable thresholds for VT2 x V(REGN) and VT3 x V(REGN). The thresholds for VT2 x V(REGN) and VT3 x V(REGN) are controlled by TS_COOL and TS_WARM. This programmability gives more flexibility for the configuration of the JEITA profile. Select T1=0°C and T5=60°C for Li-ion or Li-polymer battery, the RT1 and RT2 are calculated to be 5.24KΩ and 30.31KΩ respectively.