SLUSDV2A May 2020 – May 2021 BQ25798
After the REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements in order to move forward to the next power on steps.
Once the conditions are met, the status register bit PG_STAT is set high and the INT pin is pulsed to signal the host.
If VBUS_OVP is detected (failing condition 1 above), an INT pulse is asserted to alert the host if the VBUS_OVP_MASK = 0 or the PG_MASK = 0. The VBUS_OVP_STAT and VBUS_OV_FLAG fault registers get set, and the PG_STAT bit remains low. The device automatically retries input source qualification once the over-voltage fault goes away.
If a poor source is detected (when pulling IPOORSRC, the VBUS voltage drops below VPOORSRC), the EN_HIZ bit is set to 1, PG_STAT bit remains low, PG_FLAG will be set to 1, and an INT pulse will be asserted if PG_MASK = 0. The device will repeat the poor source qualification routine every 7 minutes until either the adapter is removed or the source is qualified. Each failed poor source qualification will cause EN_HIZ and PG_FLAG to be set to 1, and an INT pulse will be asserted if PG_MASK = 0. In the 7 minute interim between poor source qualification attempts, the host may set EN_HIZ = 0 to force an immediate retry of the poor source qualification. The EN_HIZ bit is cleared automatically when the adapter is plugged in, so cycling the adapter will also force an immediate retry of the poor source qualification.