SLVSE40C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
The device includes a 16-bit ADC to monitor critical system information based on the device’s modes of operation. The control of the ADC is done through the ADC Control Register (Address = 15h) [reset = 30h] register. The ADC_EN bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows continuous conversion or one-shot behavior. After a 1-shot conversion finishes, the ADC_EN bit is cleared, and must be re-asserted to start a new conversion.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either the VVBUS>VVBUS_UVLOZ or VBAT>VBAT_UVLOZ is valid. If no adapter is present, and the VBAT is less than VBAT_UVLOZ, the device will not perform an ADC measurement, nor update the ADC read-back values in REG17 through REG24. Additionally, the device will immediately reset ADC_EN bit without sending any interrupt. The same will happen if the ADC is enabled when all ADC channels are disabled. It is recommended to read back ADC_EN after setting it to '1' to ensure ADC is running a conversion. If the charger changes mode (for example, if adapter is connected, EN_HIZ goes to '1', or EN_OTG goes to '1') while an ADC conversion is running, the conversion is interrupted. Once the mode change is complete, the ADC resumes conversion, starting with the channel where it was interrupted.
The ADC_SAMPLE bits control the sample speed of the ADC, with conversion time of tADC_CONV. The integrated ADC has two rate conversion options: a 1-shot mode and a continuous conversion mode set by the ADC_RATE bit. By default, all ADC parameters will be converted in 1-shot or continuous conversion mode unless disabled in the ADC Function Disable Register (Address = 16h) [reset = 00h]. If an ADC parameter is disabled by setting the corresponding bit in REG16, then the read-back value in the corresponding register will be from the last valid ADC conversion or the default POR value (all zeros if no conversions have taken place). If an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish the conversion of that parameter, but will not convert the parameter starting the next conversion cycle. Even though no conversion takes place when all ADC measurement parameters are disabled, the ADC circuitry is active and ready to begin conversion as soon as one of the bits in the ADC Function Disable register is set to ‘0’. If all channels are disabled in 1-shot conversion mode, the ADC_EN bit is cleared.
The ADC_DONE_STAT and ADC_DONE_FLAG bits signal when a conversion is complete in 1-shot mode only. This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous conversion mode, the ADC_DONE_STAT bit has no meaning and will be '0'. The ADC_DONE_FLAG bit will remain unchanged in continuous conversion mode.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set ADC_EN = ‘0’ to disable the ADC. ADC conversion is interrupted upon adapter plug-in, and will only resume until after Input Source Type Detection is complete. ADC readings are only valid for DC states and not for transients. When host writes ADC_EN = 0, the ADC stops immediately, and ADC measurement values correspond to last valid ADC reading.
If the host wants to exit ADC more gracefully, it is possible to do either of the following: