SLUSE31A Data sheet

SLUSE31A April 2020 – February 2021 BQ25968

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

YFF|56
- MXBG330

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.5 Electrical Characteristics

over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_{Q_VBUS}	VBUS Operating Quiescent Current	ADC Disabled, Charge Disabled, OVPGATE not used		285		µA
		ADC Disabled, Charge Disabled, OVPGATE used		345		µA
		ADC Enabled (fastest mode), Charge Disabled		400		µA
		ADC Enabled (slowest mode), Charge Disabled		385		µA
I_{Q_BAT}	Battery Only Quiescent Current	ADC Disabled, Charge Disabled, VIN Not Present		8	18	µA
		ADC Enabled (slowest mode), Charge Disabled, VBUS Not Present		385		µA
		ADC Enabled (fastest mode), Charge Disabled, VBUS Not Present		385		µA
RESISTANCES
R_{QB_ON}	VBUS to PMID On Resistance	VBUS = 9 V		6	8	mΩ
R_{QCH1_ON}	On resistance of QCH1	VPMID = 9 V		22	27	mΩ
R_{QDH1_ON}	On resistance of QDH1	CFLY = 4.5 V		10	16	mΩ
R_{QCL1_ON}	On resistance of QCL1	VOUT = 4.5 V		7	14	mΩ
R_{QDL1_ON}	On resistance of QDL1	CFLY = 4.5 V		8	14	mΩ
R_{QCH2_ON}	On resistance of QCH2	VPMID = 9 V		22	27	mΩ
R_{QDH2_ON}	On resistance of QDH2	CFLY = 4.5 V		10	16	mΩ
R_{QCL2_ON}	On resistance of QCL2	VOUT = 4.5 V		7	14	mΩ
R_{QDL2_ON}	On resistance of QDL2	CFLY = 4.5 V		8	14	mΩ
R_{VBUS_PD}	VBUS pull-down resistance			6		kΩ
R_{VAC_PD}	VAC pull-down resistance			130		Ω
INTERNAL THRESHOLDS
VBUS_UVLO	Rising	VBUS Rising			3.3	V
VAC_UVLO	Rising	VAC Rising			3.3	V
VAC_UVLO	Falling Hysteresis			300		mV
V_OVPGATE	External FET Gate Drive Voltage, Measured from Gate to Source, with minimum 8 nF CGS	VAC = 8 V		10		V
VOUT_UVLO	Rising				2.3	V
VOUT_UVLO	Falling Hysteresis			100		mV
VAC_PRESENT	Rising				3.5	V
VAC_PRESENT	Falling Hysteresis			300		mV
VBUS_PRESENT	Rising				2.85	V
VBUS_PRESENT	Falling Hysteresis			500		mV
VOUT_PRESENT	Rising			2.3	2.85	V
VOUT_PRESENT	Falling Hysteresis			100		mV
T_SHUT	Rising Internal (TJ) Shutdown			150		°C
T_SHUT	Falling Hysteresis			30		°C
PROTECTION and ALARMS THRESHOLD AND ACCURACY
V_OUTOVP	VOUT OVP rising threshold		4.8	4.9	5	V
V_DROP	VDROP rising threshold	Adjustable in Register 0x05h, bit 4 = 0		300		mV
V_DROP	VDROP rising threshold	Adjustable in Register 0x05h, bit 4 = 1		400		mV
V_BATOVP	VBAT Over-Voltage Range	Adjustable in Register 0x00h	4.2		4.65	V
	VBAT Over-Voltage Step Size			10		mV
	VBAT Over-Voltage Accuracy		–1%		1%
V_{BAT_ALM}	VBAT Alarm Range	Adjustable in Register 0x01h	4.2		4.65	V
	VBAT Alarm Step Size	Adjustable in Register 0x01h		25		mV
	VBAT Alarm Hysteresis	Falling		50		mV
	VBAT Alarm Comparator Accuracy	From VBAT = 3.5 V to 4.4 V	–0.4%		0.4%
I_{BAT_OCP}	IBAT_OCP Range	Adjustable in Register 0x02h	0		10	A
	IBAT_OCP Step Size			50		mA
	IBAT_OCP Comparator Accuracy	IBAT = 6 A	–5%		5%
I_{BATOCP_ALM}	IBATOCP_ALM Range	Adjustable in Register 0x03h	0		10	A
	IBATOCP_ALM Step Size			50		mA
	IBATOCP_ALM Hysteresis	Falling		50		mA
	IBATOCP_ALM Comparator Accuracy	IBAT = 6 A and 9 A	–1%		1%
I_{BATUCP_ALM}	IBATUCP_ALM Range	Adjustable in Register 0x04h	0		10	A
	IBATUCP_ALM Step Size			50		mA
	IBAT_UCP_ALM Hysteresis	Rising		50		mA
	IBATUCP_ALM Comparator Accuracy	IBAT = 3 A	–2%		2%
V_{VAC_OVP}	VAC_OVP Range	Adjustable in Register 0x05h	6.5		17	V
	VAC_OVP Step Size	Step size valid for 11 V through 17 V only		1		V
	VAC_OVP Comparator Accuracy	Accuracy for 6.5 V	–2%		2%
	VAC_OVP Comparator Accuracy	Accuracy for 11 V through 17 V	–2%		2%
V_{BUS_OVP}	VBUS_OVP Range	Adjustable in Register 0x06h, 250 mV typical hysteresis	6		12.35	V
	VBUS_OVP Step Size			50		mV
	VBUS_OVP Comparator Accuracy	VBUS = 10 V	–1%		1%
V_{BUSOVP_ALM}	VBUSOVP_ALM Range	Adjustable in Register 0x07h	6		12.35	mV
	VBUSOVP_ALM Step Size			50		mV
	VBUSOVP_ALM Hysteresis	Falling		50		mV
	VBUSOVP_ALM Comparator Accuracy		–0.5%		0.5%
I_{BUS_OCP}	IBUS_OCP Range	Adjustable in Register 0x08h	0		4.75	A
	IBUS_OCP Step Size			50		mA
	IBUS_OCP Comparator Accuracy	3 A	–5%		5%
I_{BUS_UCP}	IBUS_UCP Rising, IBAT must reach this value before the SS timeout or Switching Stops, Protection disabled until IBUS Current Reaches this Value	Adjustable in Register 0x2Bh, bit 2 = 0		300	375	mA
I_{BUS_UCP}	IBUS_UCP Rising, IBAT must reach this value before the SS timeout or Switching Stops, Protection disabled until IBUS Current Reaches this Value	Adjustable in Register 0x2Bh, bit 2 = 1		500	575	mA
I_{BUS_UCP}	IBUS_UCP Falling, Switching stops when IBUS current reaches this value	Adjustable in Register 0x2Bh, bit 2 = 0	10	150		mA
I_{BUS_UCP}	IBUS_UCP Falling, Switching stops when IBUS current reaches this value	Adjustable in Register 0x2Bh, bit 2 = 1	100	250		mA
I_{BUSOCP_ALM}	IBUSOCP_ALM Range	Adjustable in Register 0x09h	0		4.95	A
	IBUSOCP_ALM Step Size			50		mA
	IBUSOCP_ALM Hysteresis	Falling		50		mA
	IBUSOCP_ALM Comparator Accuracy	IBUS = 3 A (0°C to 85°C)	–4%		4%
TS_{BAT_FLT} TS_{BUS_FLT}	TSBUS and TSBAT voltage range		0%		75%
	TSBUS and TSBAT Threshold Step Size		0%		0.1953%
	TSBUS and TSBAT Comparator Accuracy		–1%		1%
	TSBUS and TSBAT Falling Hysteresis			4%
TIMINGS
f_SW	Switching Frequency	Register set to 500 kHz in Register 0x0Bh		500		kHz
t_{VAC_OVP}	VAC OVP reaction time			0.1		µs
t_{VOUT_OVP}	VAC OVP reaction time			5.5		µs
t_{VAC_PD}	VAC Pulldown duration			400		ms
t_{VBUS_OVP}	VBUS OVP reaction time (Note: The deglitch time is increased during regulation)	Not in regulation		1		µs
t_{IBUS_OCP}	IBUS OCP reaction time (Note: The deglitch time is increased during regulation)	Not in regulation		75		µs
t_{IBUS_UCP}	IBUS UCP falling reaction time (Note: The deglitch time is increased during regulation)	Not in regulation. Adjustable in Register 0x2Eh, bit 4 = 0		10		µs
t_{IBUS_UCP}	IBUS UCP falling reaction time (Note: The deglitch time is increased during regulation)	Not in regulation. Adjustable in Register 0x2Eh, bit 4 = 1		10		ms
t_VDROP	VDROP rising threshold deglitch (Note: The deglitch time is increased during regulation)	Not in regulation. Adjustable in Register 0x2Eh, bit 3 = 0		10		µs
t_VDROP	VDROP rising threshold deglitch (Note: The deglitch time is increased during regulation)	Not in regulation. Adjustable in Register 0x2Eh, bit 3 = 1		5		ms
t_{VBAT_OVP}	VBAT OVP reaction time			0		µs
t_{VBAT_OVP}	VBAT OVP reaction time	Deglitch during regulation		5		ms
t_{VOUT_OVP}	VOUT OVP reaction time			4		µs
t_{IBAT_OCP}	IBAT OCP reaction time			500		µs
t_{IBAT_OCP}	IBAT OCP reaction time	Deglitch during regulation		5		ms
t_INT	Duration that INT is pulled low when an event occurs			256		µs
t_{REG_TIMEOUT}	If the part is in regulation, but below V_{DROP_OVP} for this amount of time, the part will stop switching.			650		ms
t_{INT_REG_DGL}	Deglitch when INT is pulled low after an event occurs	Rising		100		ms
t_{INT_REG_DGL}	Deglitch when INT is pulled low after an event occurs	Falling		5		ms
T_{ALM_DEBOUNCE}	Time between consecutive faults for ALM indication			120		ms
t_{BUS_DETACH}	IBUS threshold reaction time			1		µs
ADC MEASUREMENT ACCURACY AND PERFORMANCE
t_{ADC_CONV}	Conversion Time, Each Measurement	ADC_SAMPLE[1:0] = 00		24		ms
		ADC_SAMPLE[1:0] = 01		12
		ADC_SAMPLE[1:0] = 10		6
		ADC_SAMPLE[1:0] = 11		3
ADC_RES	Effective Resolution (0°C to 85°C)	ADC_SAMPLE[1:0] = 00		14		bits
		ADC_SAMPLE[1:0] = 01		13
		ADC_SAMPLE[1:0] = 10		12
		ADC_SAMPLE[1:0] = 11		11
ADC MEASUREMENT RANGES AND LSB
IBUS_ADC	ADC Bus Current Readable in Registers 0x16h and 0x17h	Range	0		5	A
IBUS_ADC	ADC Bus Current Readable in Registers 0x16h and 0x17h	LSB		1		mA
IBUS_ADC	ADC Accuracy	1.5 A (0°C to 85°C)	–5%		5%
IBUS_ADC	ADC Accuracy	3 A (0°C to 85°C)	–5%		5%
VBUS_ADC	ADC Bus Voltage Readable in Registers 0x18h and 0x19h	Range	0		14	V
VBUS_ADC	ADC Bus Voltage Readable in Registers 0x18h and 0x19h	LSB		1		mV
VBUS_ADC	ADC Bus Voltage	Accuracy for 8V, ADC_RATE = 00	–0.%5		0.5%
VAC_ADC	ADC VAC Voltage Readable in Registers 0x1Ah and 0x1Bh	Range	0		14	V
VAC_ADC	ADC VAC Voltage Readable in Registers 0x1Ah and 0x1Bh	LSB		1		mV
VAC_ADC	ADC VAC Voltage	Accuracy for 8 V, ADC_RATE = 00	–0.5%		0.5%
VOUT_ADC	ADC Output Voltage Readable in Registers 0x1Ch and 0x1Dh	Range	0		5	V
VOUT_ADC	ADC Output Voltage Readable in Registers 0x1Ch and 0x1Dh	LSB		1		mV
VOUT_ADC	ADC Output Voltage	Accuracy for 4 V, ADC_RATE = 00	–0.5%		0.5%
VBAT_ADC	ADC Battery Voltage Readable in Registers 0x1Eh and 0x1Fh	Range	0		5	V
VBAT_ADC	ADC Battery Voltage Readable in Registers 0x1Eh and 0x1Fh	LSB		1		mV
VBAT_ADC	ADC Battery Voltage	Accuracy for 3.5 V through 4.4 V, ADC_RATE = 00	–0.4%		0.2%
IBAT_ADC	ADC Battery Current Readable in Registers 0x20h and 0x21h	Range	0		10	A
IBAT_ADC	ADC Battery Current Readable in Registers 0x20h and 0x21h	LSB with 2 mΩ R_SENSE		1		mA
IBAT_ADC	ADC Battery Current	3 A	–2%		2%
IBAT_ADC	ADC Battery Current	6 A	–1.5%		1.5%
IBAT_ADC	ADC Battery Current	9 A	–1.5%		1.5%
TSBUS_ADC	ADC TSBUS pin voltage	Range	0.2		2.7	V
TSBUS_ADC	ADC TSBUS % of VOUT Readable in Registers 0x22h and 0x23h	Range	0%		50%
TSBUS_ADC	ADC TSBUS % of VOUT Readable in Registers 0x22h and 0x23h	LSB		0.09766%
TSBUS_ADC	ADC TSBUS Accuracy	TSBUS pin voltage 2 V	–1%		1%
TSBAT_ADC	ADC TSBAT pin voltage	Range	0.2		2.7	V
TSBAT_ADC	ADC TSBAT pin voltage Readable in Registers 0x24h and 0x25h	Range	0%		50%
TSBAT_ADC	ADC TSBAT pin voltage Readable in Registers 0x24h and 0x25h	LSB		0.09766%
TSBAT_ADC	ADC TSBAT pin voltage	TSBAT pin voltage 2 V	–1%		1%
TDIE_ADC	ADC Die Temperature Readable in Registers 0x26h and 0x27h	Range	–40		150	°C
TDIE_ADC	ADC Die Temperature Readable in Registers 0x26h and 0x27h	LSB		0.5		°C
TDIE_ADC	ADC Die Temperature (Typ over temp)			±4		°C
REGN LDO
V_REGN	REGN LDO Output Voltage	VBUS = 8 V		5		V
I_REGN	REGN LDO Current Limit	VBUS = 8 V, VREGN = 4.5 V	50			mA
LOGIC I/O THRESHOLDS ( INT, BATP_SYNCIN)
V_IL	Input Low Threshold	I_SINK = 5 mA			0.4	V
V_IH	Input High Threshold	I_SINK = 5 mA	1.3			V
I_LEAK	High Level Leakage Current	V_PULL-UP = 3.3 V			1	µA
LOGIC I/O THRESHOLDS (TSBAT_SYNCOUT)
V_OH	Output High Threshold	V_PULL-UP = 1.8V	1.3
V_OL	Output Low Threshold	V_PULL-UP = 1.8V			0.4
I2C LEVELS and TIMINGS
V_IL	Input Low Threshold	V_PULL-UP = 1.8 V, SDA and SCL			0.4	V
V_IH	Input High Threshold	V_PULL-UP = 1.8 V, SDA and SCL	1.3			V
V_OL	Output Low Threshold	I_OL = 20 mA			0.4	V
I_BIAS	High Level Leakage Current	V_PULL-UP = 1.8 V, SDA and SCL			1	µA
f_SCL	SCL Clock Frequency				1	MHz
t_{SU_STA}	Data Set-Up Time		10			ns
t_{HD_DAT}	Data Hold Time		0		70	ns
t_rDA	Rise Time of SDA Signal	Cbus = 100 pF max	10		80	ns
t_fDA	Fall Time of SDA Signal	Cbus = 100 pF max	10		80	ns