SLUSE31A April   2020  – February 2021 BQ25968

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charging System
      2. 9.3.2  Battery Charging Profile
      3. 9.3.3  Control State Diagram for System Implementation
      4. 9.3.4  Device Power Up
      5. 9.3.5  Switched Cap Function
        1. 9.3.5.1 Theory of Operation
      6. 9.3.6  Charging Start-Up
      7. 9.3.7  Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
      8. 9.3.8  Device Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
      9. 9.3.9  INT Pin, STAT, FLAG, and MASK Registers
      10. 9.3.10 CDRVH and CDRVL_ADDRMS Functions
      11. 9.3.11 Parallel Operation Using Master and Slave Modes
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Modes and Protection Status
        1. 9.4.1.1 Input Overvoltage, Overcurrent, Undercurrent and Short-Circuit Protection
        2. 9.4.1.2 Battery Overvoltage and Overcurrent Protection
        3. 9.4.1.3 Cycle-by-Cycle Current Limit
    5. 9.5 Programming
      1. 9.5.1 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1 Customer Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Standalone Application Information (for use with switching charger)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Parallel BQ25968 for Higher Power Applications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1.1 Input Overvoltage, Overcurrent, Undercurrent and Short-Circuit Protection

The device integrates the functionality of an input overvoltage protector. The device can be paired with an external N-channel FET to block input voltages higher than the setting programmed by the ADDR_MS pin. The device senses the input through the VAC pin and turns the external N-channel FET on or off through the OVPGATE pin. This eliminates the need for a separate OVP device to protect the overall system. The integrated VAC_OVP feature has a reaction time of tVAC_OVP. The VAC OVP setting is adjustable in the VAC_PROTECTION register.

The integrated OVP feature has a reaction time of tVAC_OVP (the actual time to turn off OVP FET will be longer and depends upon the FET gate capacitance) and the feature is always active as long as VVAC > VACPRESENT).

The default VAC OVP threshold is set by CDRVL_ADDRMS and can be changed with the VAC_PROTECTION register bits. VAC OVP bits are only reset by a REG_RST or a POR event where the CDRVL_ADDRMS value is used.

GUID-AEF7C89F-7B96-4E32-9D63-256BDDB106B0-low.gifFigure 9-8 OVPGATE Timing

The device has an integrated blocking FET (QB), with a reaction time of tVBUS_OVP. The BUS OVP threshold is adjustable in the BUS_OVP register.

Overcurrent protection monitors the current flow into VBUS. The overcurrent protection threshold is adjustable in the BUS_OCP register through the BUS_OCP bits, with a reaction time of tIBUS_OCP.

When any input OVP, UVP, or OCP event is triggered, the CHG_EN bit is set to ‘0’ to disable charging, and the start-up protocol must be followed to begin charging again.

When the BAT_UCP_ALM is triggered, the host is notified and the CHG_EN bit is not set to ‘0’ to disable charging. The host must disable charging after this event and determine when to switch back to the primary switching charger. This alarm is blanked during start up for proper operation. When the device starts switching, the IBUS_UCP protection is disabled until the BUS current rises above IBUS_UCP rising threshold. After that, if the BUS current falls below IBUS_UCP falling, the device will stop switching. IBUS_UCP falling threshold cannot be masked or disabled.