SLUSBU5 Data sheet

SLUSBU5V November 2013 – September 2025 BQ2961 , BQ2962

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DSG|8
- MPDS308C

Thermal pad, mechanical data (Package|Pins)

DSG|8
- QFND141I

Orderable Information

6.5 Electrical Characteristics

Typical values stated where T_A = 25°C and VDD = 14.4V, MIN/MAX values stated where T_A = –40°C to +110°C, and V_DD = 3V to 15V (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
Voltage Protection Thresholds
V_OV	V_(PROTECT) Overvoltage Detection	R_IN = 1 kΩ		Applicable Voltage: 3.85V to 4.6V in 50mV steps			V
V_HYS	OV Detection Hysteresis			250	300	400	mV
V_OA	OV Detection Accuracy	T_A = 25°C		–10		10	mV
V_OADRIFT	OV Detection Accuracy Across Temperature	T_A = –40°C		–40		40	mV
		T_A = 0°C		–20		20	mV
		T_A = 60°C		–24		24	mV
		T_A = 110°C		–54		54	mV
		T_A = 110°C		–54		54	mV
Supply and Leakage Current
I_DD	Supply Current with REG on	(V_n – V_n-1) = 2V to 4.15V, n = 1 to 4, VDD = top V_n voltage (V1 – V_SS) > V_UVREG , I_REG = 0mA,	T_A = 0°C to 60°C		4	6	µA
I_DD	Supply Current with REG on		T_A = –40°C to 110°C			8	µA
I_DD	Supply Current with REG off	(V_n – V_n-1) = 2V to 4.15V, n = 1 to 4, VDD = top V_n voltage (V1 – V_SS) < V_UVREG	T_A = 0°C to 60°C		1	2	µA
I_DD	Supply Current with REG off		T_A = –40°C to 110°C			4	µA
I_IN	Input Current at V_x Pins	(V_n – V_n-1) = (V1 – V_SS) = 3.8V, VDD = top V_n voltage, T_A = 25°C		–0.1		0.1	µA
Output Drive OUT, CMOS Active High
V_OUT	Output Drive Voltage, Active High	(V_n – V_n-1) or (V1 – V_SS) > V_OV, I_OH = 100µA, VDD = top V_n voltage		6	7	8	V
		If three of four cells are short circuited, only one cell remains powered and > V_OV, VDD = V_n (the remaining cell voltage), I_OH = 100µA			VDD – 0.3		V
		(V_n – V_n-1) and (V1 – V_SS) < V_OV, VDD = sum of the cell stack voltage, I_OL = 100µA measured into OUT pin			250	400	mV
I_OUTH	OUT Source Current (during OV)	(V_n – V_n-1), (V3 – V2), or (V1 – V_SS) > V_OV, VDD = top V_n voltage, forced OUT = 0V, measured out of OUT pin				4.5	mA
I_OUTL	OUT Sink Current (no OV)	(V_n – V_n-1) and (V1 – V_SS) < V_OV, VDD = top V_n voltage, forced OUT = VDD, measured into OUT pin. Pull-up resistor R_PU = 5kΩ to VDD		0.5		14	mA
Internal Fixed Delay Timer
t_DELAY	OV Delay Time⁽¹⁾	Internal Fixed Delay, 3-s delay option		2.4	3	3.6	s
		Internal Fixed Delay, 4-s delay option		3.2	4	4.8	s
		Internal Fixed Delay, 5.5-s delay option		4.4	5.5	6.6	s
		Internal Fixed Delay, 6.5-s delay option		5.2	6.5	7.8	s
t_{DELAY_CTM}	Fault Detection Delay Time in Test Mode OV Delay Time	Internal Fixed Delay			15		ms
t_{DELAY_RESET}	OV delay timer count reset time; t_DELAY resets when the cell voltage falls below V_OV for t_{DELAY_RESET}.⁽¹⁾	Internal Fixed Delay			0.6		ms
Regulated Supply Output, REG
V_REG	REG Supply at 500µA load	VDD ≥ 4V, I_REG = 500µA, C_REG = 0.47µF	V_REG = 3.3V,	3.234	3.300	3.366	V
			V_REG = 3.15V, BQ2962	3.087	3.150	3.213
			V_REG = 3.0V, BQ2962	2.940	3.000	3.060
			V_REG = 2.5V, BQ2961	2.450	2.500	2.550
			V_REG = 1.8V, BQ2961	1.764	1.800	1.836
V_REG	REG Supply from 0 to 2mA load	VDD ≥ 4V, I_REG = 0µA to 2mA, C_REG = 0.47µF	V_REG = 3.3V, BQ2961, BQ2962	3.200	3.300	3.400	V
			V_REG = 3.15V, BQ2962	3.050	3.150	3.250
			V_REG = 3.0V, BQ2962	2.900	3.000	3.100
			V_REG = 2.5V, BQ2961	2.425	2.500	2.575
			V_REG = 1.8V, BQ2961	1.746	1.800	1.854
I_REG	REG Current Output	VDD ≥ 4V, C_REG = 0.47µF		0		2	mA
I_{REG_ SC_Limit}	REG Output Short Circuit Current Limit	REG = V_SS, C_REG = 0.47µF		4			mA
R_{REG_ PD}	REG pull-down resistor	REG is disabled.		20	30	45	kΩ
Regulated Supply Undervoltage Self-Disable
V_UVREG	Undervoltage detection	Factory Configuration: 2.0V to 3.5V in 50mV steps, T_A = 25°C		–50		50	mV
V_UVHYS	Undervoltage Detection Hysteresis			250	300	400	mV
t_UVDELAY	Undervoltage Detection Delay			4.5	6	7.5	s
V_UVQUAL	Cell voltage to qualify for UV detection				0.5		V

(1) Specified by design. Not 100% tested in production.