SLUSCS3J October   2017  – December 2022 BQ2980 , BQ2982

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Configurability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Overvoltage (OV) Status
      2. 8.3.2 Undervoltage (UV) Status
      3. 8.3.3 Overcurrent in Charge (OCC) Status
      4. 8.3.4 Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) Status
      5. 8.3.5 Overtemperature (OT) Status
      6. 8.3.6 Charge and Discharge Driver
      7. 8.3.7 CTR for FET Override and Device Shutdown
      8. 8.3.8 CTR for PTC Connection
      9. 8.3.9 ZVCHG (0-V Charging)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On-Reset (POR)
        2. 8.4.1.2 NORMAL Mode
        3. 8.4.1.3 FAULT Mode
        4. 8.4.1.4 SHUTDOWN Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Test Circuits for Device Evaluation
      2. 9.1.2 Test Circuit Diagrams
      3. 9.1.3 Using CTR as FET Driver On/Off Control
    2. 9.2 Typical Applications
      1. 9.2.1 BQ298x Configuration 1: System-Controlled Reset/Shutdown Function
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Selection of Power FET
        4. 9.2.1.4 Application Curves
      2. 9.2.2 BQ298x Configuration 2: CTR Function Disabled
      3. 9.2.3 BQ298x Configuration 3: PTC Thermistor Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Typical values stated at TA = 25°C and VDD = 3.6 V. MIN/MAX values stated with TA = –40°C to +85°C and VDD = 3 to 5 V unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT CONSUMPTION
INORMALNormal mode supply currentVCHG and VDSG > 5 V, CLOAD = 8 nF (typical 20 nA(1)), VDD > 4.0 V58µA
VCHG and VDSG > 5 V, CLOAD = 8 nF (typical 20 nA(1)), UVP < VDD < 3.9 V46µA
IFETOFFSupply current with both FET drivers offVCHG = VDSG ≤ 0.2 V24µA
ISHUTShutdown currentVPACK < VBAT, VDD = 1.5 V0.1µA
N-CH FET DRIVER, CHG and DSG
AFETONFET driver gain factor, the Vgs voltage to FETVCHG or VDSG = VDD + VDD × AFETON
UVP < VDD < 3.9 V
CLOAD = 8 nF		1.651.751.81V/V
VCHG or VDSG = VDD + VDD × AFETON
VDD > 4.0 V
CLOAD = 8 nF		1.451.551.68V/V
VFETOFFFET driver off output voltageVFETOFF = VCHG – VSS or VDSG – VSS
CLOAD = 8 nF		0.2V
VDRIVER_SHUTFET driver charge pump shut down voltageCharge pump enabled when VDD rises to VDRIVER_SHUT1.9522.1V
VDRIVER_SHUT_HYS FET driver charge pump shut down voltage hysteresis Charge pump disabled when VDD falls to VDRIVER_SHUT – VDRIVER_SHUT_HYS 50 mV
trise(2)FET driver rise timeCLOAD = 8 nF,
VCHG or VDSG rises from VDD to (2 × VDD)		400800µs
tfallFET driver fall timeCLOAD = 8 nF,
VCHG or VDSG fall to VFETOFF		50200µs
ILOADFET driver maximum loading10µA
VOLTAGE PROTECTION
VOVPOvervoltage detection rangeFactory configured, 50-mV step37505200mV
VOVP_ACCOvervoltage detection accuracyTA = 25°C, CHG/DSG CLOAD < 1 µA–1010mV
TA = 0°C to 60°C, CHG/DSG CLOAD < 1 µA–1515
TA = –40°C to +85°C, CHG/DSG CLOAD < 1 µA–2525
VOVP_HYSOvervoltage release hysteresis voltageFixed at 200 mV150200250mV
VUVPUndervoltage detection rangeFactory configured, 50-mV step22003000mV
VUVP_ACCUndervoltage detection accuracyTA = 25°C–2020mV
TA = 0°C to 60°C–3030mV
TA = –40°C to +85°C–5050mV
VUVP_HYSUndervoltage release hysteresis voltageFixed at 200 mV150200250mV
RPACK-VSSResistance between PACK and VSS during UV fault100300550kΩ
CURRENT PROTECTION
VOCOvercurrent in charge (OCC) and discharge (OCD) rangeFactory configured, 2-mV step. For OCC, the range is negative (min = –64, max = –4).464mV
VSCDShort circuit in discharge thresholdFactory configured10mV
20
30
40
60
120
200
VOC_ACCOvercurrent (OCC, OCD1, OCD2, SCD) detection accuracy< 20 mV–11mV
20 to approximately 55 mV–323
56 to approximately 100 mV–55
> 100 mV–1212
IPACK-VDDCurrent sink between PACK and VDD during current fault. Used for load removal detection824µA
IOCD_RECOCD, SCD recovery detection currentSum of current from VDD and BAT during OCD or SCD fault55µA
VOC_RELOCC fault release threshold(VBAT – VPACK)100mV
OCD, SCD fault release threshold(VPACK – VBAT)–400mV
OVERTEMPERATURE PROTECTION(2)
TOTInternal overtemperature thresholdFactory configured75°C
85
TOT_ACCInternal overtemperature detection accuracy–1010°C
TOT_HYSInternal overtemperature hysteresis81522°C
PROTECTION DELAY(2)
tOVPOvervoltage detection delayFactory configured0.20.250.3s
0.811.2
11.251.5
3.64.55.4
tUVPUndervoltage detection delayFactory configured162024ms
76.896115.2
100125150
115.2144172.8
tOCOvercurrent (OCC, OCD) detection delayFactory configured5.6810.5ms
12.41619.6
162024
38.44857.6
tSCDShort circuit discharge detection delayFixed configuration125250375µs
tOTOvertemperature detection delayFixed configuration3.64.55.4s
FET OVERRIDE/DEVICE SHUTDOWN CONTROL, CTR
VIHHigh-level input1V
VILLow-level input0.4V
VHYSHysteresis for VIH and VIL200mV
RPULL_UPEffective Internal pull-up resistance (to use with external PTC)Factory configured if enabled1.5MΩ
5
8
ZVCHG (0-V Charging)
V0CHGRCharger voltage requires to start 0-V chargingBQ2980xy only (ZVCHG is disabled in BQ2982xy). The CHG driver becomes high impedance when VDD < V0INH. 2V
V0INHBattery voltage that inhibits 0-V charging1V
(1) INORMAL is impacted by the efficiency of the charge pump driving the CHG and DSG FETs. An ultra-low-gate-leakage FET may be required. INORMAL can be significantly higher with FETs with typical IGSS values of 10 µA. See Selection of Power FET for more details.
(2) Specified by design.