SLUSCS3J October   2017  – December 2022 BQ2980 , BQ2982

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Configurability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Overvoltage (OV) Status
      2. 8.3.2 Undervoltage (UV) Status
      3. 8.3.3 Overcurrent in Charge (OCC) Status
      4. 8.3.4 Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) Status
      5. 8.3.5 Overtemperature (OT) Status
      6. 8.3.6 Charge and Discharge Driver
      7. 8.3.7 CTR for FET Override and Device Shutdown
      8. 8.3.8 CTR for PTC Connection
      9. 8.3.9 ZVCHG (0-V Charging)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On-Reset (POR)
        2. 8.4.1.2 NORMAL Mode
        3. 8.4.1.3 FAULT Mode
        4. 8.4.1.4 SHUTDOWN Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Test Circuits for Device Evaluation
      2. 9.1.2 Test Circuit Diagrams
      3. 9.1.3 Using CTR as FET Driver On/Off Control
    2. 9.2 Typical Applications
      1. 9.2.1 BQ298x Configuration 1: System-Controlled Reset/Shutdown Function
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Selection of Power FET
        4. 9.2.1.4 Application Curves
      2. 9.2.2 BQ298x Configuration 2: CTR Function Disabled
      3. 9.2.3 BQ298x Configuration 3: PTC Thermistor Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.3 Using CTR as FET Driver On/Off Control

Normally, CTR is not designed as a purely on/off control of the FET drivers, because there is a timing constriction on the pin. The following is a list of workarounds to implement the CTR as an on/off switch to the FET drivers.

  1. Switching CTR from high to low with less than 3.6 s:

    If the application only requires turning off the FET drivers in < 3.6 s, then the CTR pin can simply be viewed as an on/off switch of the FET drivers. That means, after the CTR pin is pulled high, the application will pull the CTR pin back low in < 3.6 s.

  2. Applying a voltage on PACK to prevent the device from entering SHUTDOWN mode:

    When the CTR pin is be pulled high for > 3.6 s, there is a chance the device may go into SHUTDOWN mode. If the CTR pin is high for > 5.4 s, the device will be in SHUTDOWN mode. For applications that may use the CTR to keep the FET drivers off for > 3.6 s, the workaround is to keep VPACK within the VDD recommended operating range while the CTR is pulled high to prevent the device from entering SHUTDOWN mode. The device is forced to stay in NORMAL mode with this method.

    Because the PACK pin is also connected to the PACK terminal, the system designer should have a blocking diode to protect the GPIO (that controls the CTR pin) from high voltage.

GUID-4815AB72-B3FF-47CD-AB19-A44FDEFB2181-low.gifFigure 9-5 PACK Voltage Timing with Switching CTR as On/Off Control of FET Drivers