SLUSBC8C December   2013  – July 2018

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Wireless Power Consortium (WPC or Qi) Inductive Power System
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 A Brief Description of the Wireless System
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Details of a Qi Wireless Power System and bq51003 Power Transfer Flow Diagrams
      2. 8.3.2  Dynamic Rectifier Control
      3. 8.3.3  Dynamic Efficiency Scaling
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Input Overvoltage
      6. 8.3.6  Adapter Enable Functionality and EN1/EN2 Control
      7. 8.3.7  End Power Transfer Packet (WPC Header 0x02)
      8. 8.3.8  Status Outputs
      9. 8.3.9  WPC Communication Scheme
      10. 8.3.10 Communication Modulator
      11. 8.3.11 Adaptive Communication Limit
      12. 8.3.12 Synchronous Rectification
      13. 8.3.13 Temperature Sense Resistor Network (TS)
      14. 8.3.14 3-State Driver Recommendations for the TS-CTRL Pin
      15. 8.3.15 Thermal Protection
      16. 8.3.16 WPC v1.2 Compliance – Foreign Object Detection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 bq51003 Wireless Power Receiver Used as a Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Using the bq51003 as a Wireless Power Supply
          2. 9.2.1.2.2 Series and Parallel Resonant Capacitor Selection
          3. 9.2.1.2.3 COMM, CLAMP, and BOOT Capacitors
          4. 9.2.1.2.4 Control Pins and CHG
          5. 9.2.1.2.5 Current Limit and FOD
          6. 9.2.1.2.6 RECT and OUT Capacitance
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual Power Path: Wireless Power and DC Input
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over operating free-air temperature range, 0°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO Undervoltage lockout VRECT: 0 V → 3 V 2.6 2.7 2.8 V
VHYS Hysteresis on UVLO VRECT: 3 V → 2 V 250 mV
Hysteresis on OVP VRECT: 16 V → 5 V 150 mV
VRECT-OVP Input overvoltage threshold VRECT: 5 V → 16 V 14.5 15 15.5 V
VRECT-REG Dynamic VRECT threshold 1 ILOAD < 0.1 x IIMAX (ILOAD rising) 7.08 V
Dynamic VRECT threshold 2 0.1 x IIMAX < ILOAD < 0.2 x IIMAX
(ILOAD rising)		 6.28
Dynamic VRECT threshold 3 0.2 x IIMAX < ILOAD < 0.4 x IIMAX
(ILOAD rising)		 5.53
Dynamic VRECT threshold 4 ILOAD > 0.4 x IIMAX (ILOAD rising) 5.11
VRECT TRACKING In current limit voltage above VOUT VO+0.25
ILOAD ILOAD hysteresis for dynamic VRECT thresholds as a % of IILIM ILOAD falling 4%
VRECT-DPM Rectifier undervoltage protection, restricts IOUT at VRECT-DPM 3 3.1 3.2 V
VRECT-REV Rectifier reverse voltage protection at the output VRECT-REV = VOUT – VRECT,
VOUT = 10 V		 8 9 V
QUIESCENT CURRENT
IRECT Active chip quiescent current consumption from RECT ILOAD = 0 mA, 0°C ≤ TJ ≤ 85°C 8 10 mA
ILOAD = 300 mA,
0°C ≤ TJ ≤ 85°C		 2 3 mA
IOUT Quiescent current at the output when wireless power is disabled (Standby) VOUT = 5 V, 0°C ≤ TJ ≤ 85°C 20 35 µA
ILIM SHORT CIRCUIT
RILIM Highest value of ILIM resistor considered a fault (short). Monitored for IOUT > 100 mA RILIM: 200 Ω → 50 Ω. IOUT latches off, cycle power to reset 120 Ω
tDGL Deglitch time transition from ILIM short to IOUT disable 1 ms
ILIM_SC ILIM-SHORT,OK enables the ILIM short comparator when IOUT is greater than this value ILOAD: 0 mA → 200 mA 120 145 165 mA
Hysteresis for ILIM-SHORT,OK comparator ILOAD: 0 mA → 200 mA 30 mA
IOUT Maximum output current limit, CL Maximum ILOAD that will be delivered for 1 ms when ILIM is shorted 2.45 A
OUTPUT
VOUT-REG Regulated output voltage ILOAD = 500 mA 4.96 5 5.04 V
ILOAD = 10 mA 4.97 5.01 5.05
KILIM Current programming factor for hardware protection RLIM = KILIM / IILIM, where IILIM is the hardware current limit.
IOUT = 500 mA		 303 314 321 AΩ
KIMAX Current programming factor for the nominal operating current IIMAX = KIMAX / RLIM where IMAX is the maximum normal operating current.
IOUT = 500 mA		 262 AΩ
IOUT Current limit programming range 750 mA
ICOMM Current limit during WPC communication IOUT > 300 mA IOUT + 50 mA
IOUT < 300 mA 343 378 425 mA
tHOLD Holdoff time for the communication current limit during start-up 1 s
TS / CTRL
VTS Internal TS bias voltage ITS-Bias < 100 µA (periodically driven see tTS-CTRL) 2 2.2 2.4 V
VCOLD Rising threshold VTS: 50% → 60% 56.5 58.7 60.8 %VTS-Bias
Falling hysteresis VTS: 60% → 50% 2
VHOT Falling threshold VTS: 20% → 15% 18.5 19.6 20.7
Rising hysteresis VTS: 15% → 20% 3
VCTRL CTRL pin threshold for a high VTS-CTRL: 50 → 150 mV 80 100 130 mV
CTRL pin threshold for a low VTS-CTRL: 150 → 50 mV 50 80 100
tTS-CTRL Time VTS-Bias is active when TS measurements occur Synchronous to the communication period 24 ms
tTS Deglitch time for all TS comparators 10 ms
RTS Pullup resistor for the NTC network. Pulled up to the voltage bias. 18 20 22 kΩ
THERMAL PROTECTION
TJ Thermal shutdown temperature 155 °C
Thermal shutdown hysteresis 20
OUTPUT LOGIC LEVELS ON CHG
VOL Open-drain CHG pin ISINK = 5 mA 500 mV
IOFF CHG leakage current when disabled VCHG = 20 V 1 µA
COMM PIN
RDS(ON) COMM1 and COMM2 VRECT = 2.6 V 1.5 Ω
fCOMM Signaling frequency on COMM pin 2 Kbps
IOFF Comm pin leakage current VCOMM1 = 20 V, VCOMM2 = 20 V 1 µA
CLAMP PIN
RDS(ON) CLAMP1 and CLAMP2 0.8 Ω
ADAPTER ENABLE
VAD-EN VAD rising threshold voltage. EN-UVLO VAD 0 V → 5 V 3.5 3.6 3.8 V
VAD-EN hysteresis, EN-HYS VAD 5 V → 0 V 400 mV
IAD Input leakage current VRECT = 0 V, VAD = 5 V 60 μA
RAD Pullup resistance from AD-EN to OUT when adapter mode is disabled and VOUT > VAD, EN-OUT VAD = 0 V, VOUT = 5 V 200 350 Ω
VAD Voltage difference between VAD and VAD-EN when adapter mode is enabled, EN-ON VAD = 5 V, 0°C ≤ TJ ≤ 85°C 3 4.5 5 V
SYNCHRONOUS RECTIFIER
IOUT IOUT at which the synchronous rectifier enters half synchronous mode, SYNC_EN ILOAD : 200 mA → 0 mA 80 100 130 mA
Hysteresis for IOUT,RECT-EN (full-synchronous mode enabled) ILOAD : 0 mA → 200 mA 25 mA
VHS-DIODE High-side diode drop when the rectifier is in half synchronous mode IAC-VRECT = 250 mA and
TJ = 25°C		 0.7 V
EN1 AND EN2
VIL Input low threshold for EN1 and EN2 0.4 V
VIH Input high threshold for EN1 and EN2 1.3 V
RPD EN1 and EN2 pull down resistance 200 kΩ
ADC (WPC Related Measurements and Coefficients)
IOUT SENSE Accuracy of the current sense over the load range IOUT = 300 mA - 500 mA –1.5% 0% 0.9%