SLUSBK2H October   2013  – March 2019

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1. 7.1 Versions
    2. 7.2 bq76920 Pin Diagram
      1. 7.2.1 bq76920 Pin Map
    3. 7.3 bq76930 Pin Diagram
      1. 7.3.1 bq76930 Pin Map
    4. 7.4 bq76940 Pin Diagram
      1. 7.4.1 bq76940 Pin Map
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Specifications
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Subsystems
        1. 10.3.1.1 Measurement Subsystem Overview
          1. 10.3.1.1.1 Data Transfer to the Host Controller
          2. 10.3.1.1.2 14-Bit ADC
            1. 10.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 10.3.1.1.3 16-Bit CC
          4. 10.3.1.1.4 External Thermistor
          5. 10.3.1.1.5 Die Temperature Monitor
          6. 10.3.1.1.6 16-Bit Pack Voltage
          7. 10.3.1.1.7 System Scheduler
        2. 10.3.1.2 Protection Subsystem
          1. 10.3.1.2.1 Integrated Hardware Protections
          2. 10.3.1.2.2 Reduced Test Time
        3. 10.3.1.3 Control Subsystem
          1. 10.3.1.3.1 FET Driving (CHG AND DSG)
            1. 10.3.1.3.1.1 High-Side FET Driving
          2. 10.3.1.3.2 Load Detection
          3. 10.3.1.3.3 Cell Balancing
          4. 10.3.1.3.4 Alert
          5. 10.3.1.3.5 Output LDO
        4. 10.3.1.4 Communications Subsystem
    4. 10.4 Device Functional Modes
      1. 10.4.1 NORMAL Mode
      2. 10.4.2 SHIP Mode
    5. 10.5 Register Maps
      1. 10.5.1 Register Details
      2. 10.5.2 Read-Only Registers
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Configuring Alternative Cell Counts
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Step-by-Step Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • AFE monitoring features
    • Pure digital interface
    • Internal ADC measures cell voltage, die temperature, and external thermistor
    • A separate, internal ADC measures pack current (coulomb counter)
    • Directly supports up to three thermistors (103AT)
  • Hardware protection features
    • Overcurrent in Discharge (OCD)
    • Short Circuit in Discharge (SCD)
    • Overvoltage (OV)
    • Undervoltage (UV)
    • Secondary protector fault detection
  • Additional features
    • Integrated cell balancing FETs
    • Charge, discharge low-side NCH FET drivers
    • Alert interrupt to host microcontroller
    • 2.5-V or 3.3-V output voltage regulator
    • No EEPROM programming necessary
    • High supply voltage absolute maximum (up to 108 V)
    • Simple I2C compatible interface (CRC option)
    • Random cell connection tolerant