SLUSBK2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 BQ76930 Pin Diagram

GUID-0C830BA8-8ECF-4B63-B2C2-1439A8DCAD17-low.gif
Table 6-2 BQ76930 Pin Functions
PIN NAME TYPE DESCRIPTION
1 DSG O Discharge FET driver
2 CHG O Charge FET driver
3 VSS — Chip VSS
4 SDA I/O I2C communication to the host controller
5 SCL I I2C communication to the host controller
6 TS1 I Thermistor #1 positive terminal(1)
7 CAP1 O Capacitor to VSS
8 REGOUT P Output LDO
9 REGSRC I Input source for output LDO
10 VC5X P Thermistor #2 negative terminal
11 NC — No connect (short to CAP2)
12 NC — No connect (short to CAP2)
13 TS2 I Thermistor #2 positive terminal(1)
14 CAP2 O Capacitor to VC5X
15 BAT P Battery (top-most) terminal
16 VC10 I Sense voltage for 10th cell positive terminal
17 VC9 I Sense voltage for 9th cell positive terminal
18 VC8 I Sense voltage for 8th cell positive terminal
19 VC7 I Sense voltage for 7th cell positive terminal
20 VC6 I Sense voltage for 6th cell positive terminal
21 VC5B I Sense voltage for 6th cell negative terminal
22 VC5 I Sense voltage for 5th cell positive terminal
23 VC4 I Sense voltage for 4th cell positive terminal
24 VC3 I Sense voltage for 3rd cell positive terminal
25 VC2 I Sense voltage for 2nd cell positive terminal
26 VC1 I Sense voltage for 1st cell positive terminal
27 VC0 I Sense voltage for 1st cell negative terminal
28 SRP I Negative current sense (nearest VSS)
29 SRN I Positive current sense
30 ALERT I/O Alert output and override input
(1) If not used, pull down to group ground reference (VSS for TS1 and VC5X for TS2) with a 10-kΩ nominal resistor.