SLUSBK2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.2 Read-Only Registers

Table 8-15 CELL VOLTAGE REGISTERS
VC1_HI, _LO (0x0C–0x0D), VC2_HI, _LO (0x0E–0x0F), VC3_HI, _LO (0x10–0x11), VC4_HI, _LO (0x12–0x13), VC5_HI, _LO (0x14–0x15) / BQ76930, BQ76940: VC6_HI, _LO (0x16–0x17), VC7_HI, _LO (0x18–0x19), VC8_HI, _LO (0x1A–0x1B), VC9_HI, _LO (0x1C–0x1D), VC10_HI, _LO (0x1E–0x1F) / BQ76940: VC11_HI, _LO (0x20–0x21), VC12_HI, _LO (0x22–0x23), VC13_HI, _LO (0x24–0x25), VC14_HI, _LO (0x26–0x27), VC15_HI, _LO (0x28–0x29)
BIT76543210
NAME——D13D12D11D10D9D8
RESET00000000
NAMED7D6D5D4D3D2D1D0
RESET00000000
D11:8 (Bits 3–0): Cell “x” ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): Cell ”x” ADC reading, lower 8 LSB.
Table 8-16 BAT_HI (0x2A) and BAT_LO (0x2B)
BIT76543210
NAMED15D14D13D12D11D10D9D8
RESET00000000
NAMED7D6D5D4D3D2D1D0
RESET00000000
D15:8 (Bits 7–0): BAT calculation based on adding up Cells 1–15, upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): BAT calculation based on adding up Cells 1–15, lower 8 LSB
Table 8-17 TS1_HI (0x2C) and TS1_LO (0x2D)
BIT76543210
NAME——D13D12D11D10D9D8
RESET00000000
NAMED7D6D5D4D3D2D1D0
RESET00000000
D11:8 (Bits 3–0): TS1 or DIETEMP ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): TS1 or DIETEMP ADC reading, lower 8 LSB
Table 8-18 TS2_HI (0x2E) and TS2_LO (0x2F)
BIT76543210
NAME——D13D12D11D10D9D8
RESET00000000
NAMED7D6D5D4D3D2D1D0
RESET00000000
D11:8 (Bits 3–0): TS2 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): TS2 ADC reading, lower 8 LSB
Table 8-19 TS3_HI (0x30) and TS3_LO (0x31)
BIT76543210
NAME——D13D12D11D10D9D8
RESET00000000
NAMED7D6D5D4D3D2D1D0
RESET00000000
D11:8 (Bits 3–0): TS3 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): TS3 ADC reading, lower 8 LSB
Table 8-20 CC_HI (0x32) and CC_LO (0x33)
BIT76543210
NAMECC15CC14CC13CC12CC11CC10CC9CC8
RESET00000000
NAMECC7CC6CC5CC4CC3CC2CC1CC0
RESET00000000
CC15:8 (Bits 7–0): Coulomb counter upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment).
CC7:0 (Bits 7–0): Coulomb counter lower 8 LSB
Table 8-21 ADCGAIN1 (0x50)
BIT76543210
NAME————ADCGAIN4ADCGAIN3——
RESET————————
ACCESSRRRRRRRR
Table 8-22 ADCGAIN2 (0x59)
BIT76543210
NAMEADCGAIN2ADCGAIN1ADCGAIN0—————
RESET————————
ACCESSRRRRRRRR
ADCGAIN4:3 (Bits 3–2, address 0x50):
ADC GAIN offset upper 2 MSB
ADCGAIN2:0 (Bits 7–5, address 0x59):
ADC GAIN offset lower 3 LSB
ADCGAIN<4:0> is a production-trimmed value for the ADC transfer function, in units of µV/LSB. The range is 365 µV/LSB to 396 µV/LSB, in steps of 1 µV/LSB, and may be calculated as follows:
GAIN = 365 µV/LSB + (ADCGAIN<4:0>in decimal) × (1 µV/LSB)
Alternately, a conversion table is provided below:
ADC GAINGain (µV/LSB)ADC GAINGain (µV/LSB)
0x003650x10381
0x013660x11382
0x023670x12383
0x033680x13384
0x043690x14385
0x053700x15386
0x063710x16387
0x073720x17388
0x083730x18389
0x093740x19390
0x0A3750x1A391
0x0B3760x1B392
0x0C3770x1C393
0x0D3780x1D394
0x0E3790x1E395
0x0F3800x1F396
Table 8-23 ADCOFFSET (0x51)
BIT76543210
NAMEADC OFFSET7ADC OFFSET6ADC OFFSET5ADC OFFSET4ADC OFFSET3ADC OFFSET2ADC OFFSET1ADC OFFSET0
RESET————————
ACCESSRRRRRRRR
ADCOFFSET7:0 (Bits 7–0):
ADC offset, stored in 2’s complement format in mV units. Positive full-scale range corresponds to 0x7F and negative full-scale corresponds to 0x80. The full-scale input range is –128 mV to 127 mV, with an LSB of 1 mV.
The table below shows example offsets.
ADCOFFSETOffset (mV)
0x000
0x011
0x7F127
0x80–128
0x81–127
0xFF–1