SLUSE14A December   2020  – February 2021 BQ76942


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ76942
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements – I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements – I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements – HDQ Interface
    30. 7.30 Timing Requirements – SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. Device Description
    1. 8.1 Overview
    2. 8.2 BQ76942 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications Subsystem
    3. 14.3 SPI Communications Interface
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications Interface
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
      5. 16.2.5 Design Example
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
      1. 19.2.1 Receiving Notification of Documentation Updates
    3. 19.3 Support Resources
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Applications

Figure 16-1 shows a simplified application schematic for a 10-series battery pack, using the BQ76942 together with an external secondary protector, a host microcontroller, and a communications transceiver. This configuration uses CHG and DSG FETs in series, together with high-side PFET devices used to implement precharge and predischarge functionality. See the following implementation considerations:

  • The external NPN BJT used for the REGIN preregulator can be configured with its collector routed either to the cell battery stack or the middle of the protection FETs.
  • A diode is recommended in the drain circuit of the external NPN BJT, which avoids reverse current flow from the BREG pin through the BJT base to collector in the event of a pack short circuit. This diode can be a Schottky diode if low voltage pack operation is needed; otherwise, a conventional diode can be used.
  • A series diode is recommended at the BAT pin, together with a capacitor from the pin to VSS. These components enable the device to continue operating for a short time when a pack short circuit occurs, which may cause the PACK+ and top-of-stack voltages to drop to approximately 0 V. In this case, the diode prevents the BAT pin from being pulled low with the stack, and the device will continue to operate, drawing current from the capacitor. Generally, operation is only required for a short time until the device detects the short circuit event and disables the DSG FET. A Schottky diode can be used if low voltage pack operation is needed; otherwise, a conventional diode can be used.
  • The diode in the BAT connection and the diode in the BJT collector should not be shared, because the REG0 circuit might discharge the capacitor on BAT too quickly during a short circuit event.
  • The recommended voltage range on the VC0 to VC4 pins extends to –0.2 V. This can be used, for example, to measure a differential voltage that extends slightly below ground, such as the voltage across a second sense resistor in parallel with that connected to the SRP and SRN pins.
  • If a system does not use high-side protection FETs, then the PACK pin can be connected through a series 10-kΩ resistor to the top of the stack. The LD pin can be connected to VSS. In this case, the LD pin can also be controlled separately to wake the device from SHUTDOWN mode, such as through external circuitry that holds the LD pin at the voltage of VSS while the device stays in SHUTDOWN, and to be driven above a voltage of VWAKEONLD to wake from SHUTDOWN.
  • TI recommends using 100-Ω resistors in series with the SRP and SRN pins, and a 100 nF capacitor with optional 100-pF differential filter capacitance between the pins for filtering. The routing of these components, together with the sense resistor, to the pins should be minimized and fully symmetric, with all components recommended to stay on the same side of the PCB with the device. Capacitors should not be connected from the pins to VSS.
  • Due to thermistors often being attached to cells and possibly needing long wires to connect back to the device, it may be helpful to add a capacitor from the thermistor pin to the device VSS. However, it is important to not use too large of a value of capacitor, since this will affect the settling time when the thermistor is biased and measured periodically. A rule of thumb is to keep the time constant of the circuit < 5% of the measurement time. When Settings:Configuration:Power Config[FASTADC] = 0, the measurement time is approximately 3 ms, and with [FASTADC] = 1, the measurement time is halved to approximately 1.5 ms. When using the 18-kΩ pullup resistor with the thermistor, the time constant is generally less than (18 kΩ) × C, so a capacitor less than 4 nF is recommended. When using the 180-kΩ pullup resistor, the capacitor should be less than 400 pF.
  • The integrated charge pump generates a voltage on the CP1 capacitor, requiring approximately 60 ms to charge up to approximately 11 V when first enabled using the recommended 470-nF capacitor value. When the CHG or DSG drivers are enabled, charge redistribution occurs from the CP1 capacitor to the CHG and DSG capacitive FET loads. This generally results in a brief drop in the voltage on CP1, which is then replenished by the charge pump. If the FET capacitive loading is large, such that at FET turn-on the voltage on CP1 drops below an acceptable level for the application, then the value of the CP1 capacitor can be increased. This has the drawback of requiring a longer startup time for the voltage on CP1 when the charge pump is first powered on, and so should be evaluated to ensure it is acceptable in the system. For example, if the CHG and DSG FETs are enabled simultaneously and their combined gate capacitance is approximately 400 nF, then changing CP1 to a value of 2200 nF results in the 11-V charge pump level dropping to approximately 9 V before being restored to the 11-V level by the charge pump.
GUID-86C04B23-B9E2-46B1-BF12-D1A3AD85EA6A-low.svg Figure 16-1 BQ76942 10-Series Cell Typical Implementation (Simplified Schematic)