The HDQ interface is an asynchronous
return-to-one protocol where a processor communicates with the BQ76942 device using a
single-wire connection to the ALERT pin or the HDQ pin, depending on configuration. Both the
controller (host device) and responder (BQ76942) drive the HDQ interface using an open-drain
driver with a
pullup resistor from the HDQ interface to a supply voltage required on the circuit board.
The BQ76942 device can be changed from the default communication mode to HDQ communication
mode by setting the Settings:Configuration:Comm Type configuration
sending a subcommand (at which point the device switches to HDQ mode
Note: The SWAP_COMM_MODE() subcommand immediately changes the communications interface
to that selected by the Comm Type configuration, while the
SWAP_TO_HDQ() subcommand immediately changes the interface to HDQ using the ALERT
With HDQ, the least significant bit (LSB) of
a data byte (command) or word (data) is transmitted first.
The 8-bit command code consists of two
fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit 7). The R/W
field directs the device to do one of the following:
- Accept the next 8 bits as data from the host to the device, or
- Output 8 bits of data from the device to the host in response to the
The HDQ peripheral on the BQ76942 device can
transmit and receive data as an HDQ responder only.
The return-to-one data bit frame of HDQ
consists of the following sections:
- The first section is used to start the transmission by the host sending
a Break (the host drives the HDQ interface to a logic-low state for a time
t(B)) followed by a Break Recovery (the host releases the HDQ interface for a
- The next section is for host command transmission, where the host
transmits 8 bits by driving the HDQ interface for 8 T(CYCH) time slots. For
each time slot, the HDQ line is driven low for a time T(HW0) (host writing a
"0") or T(HW1) (host writing a "1"). The HDQ pin is then released and remains
high to complete each T(CYCH) time slot.
- The next section is for data transmission where the host (if a write
was initiated) or device (if a read was initiated) transmits 8 bits by driving the HDQ
interface for 8 T(CYCH) (if host is driving) or T(CYCD) (if device
is driving) time slots. The HDQ line is driven low for a time T(HW0) (host
writing a "0"), T(HW1) (host writing a "1"), T(DW0) (device writing
a "0"), or T(DW1) (device writing a "1"). The HDQ pin is then released and
remains high to complete the time slot. The HDQ interface does not auto-increment, so a
separate transaction must be sent for each byte to be transferred.