SLUSEG7A December   2021  – June 2022 BQ77207

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 DC Characteristics
    6. 8.6 Timing Requirements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Voltage Fault Detection
      2. 9.3.2 Open Wire Fault Detection
      3. 9.3.3 Temperature Fault Detection
      4. 9.3.4 Oscillator Health Check
      5. 9.3.5 Sense Positive Input for Vx
      6. 9.3.6 Output Drive, COUT and DOUT
      7. 9.3.7 The LATCH Function
      8. 9.3.8 Supply Input, VDD
    4. 9.4 Device Functional Modes
      1. 9.4.1 NORMAL Mode
      2. 9.4.2 FAULT Mode
      3. 9.4.3 Customer Test Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Design Requirements
      2. 10.1.2 Detailed Design Procedure
        1. 10.1.2.1 Cell Connection Sequence
    2. 10.2 Systems Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 DC Characteristics

Typical values stated where TA = 25°C and VDD = 25 V, MIN/MAX values stated where TA = –40°C to 85°C and VDD = 5 V to 38.5 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVER VOLTAGE PROTECTION (OV)
VOV OV Detection Range 3.55 5.1 V
VOV_STEP OV Detection Steps 25 mV
VOV_HYS OV Detection Hysteresis  Selected OV Hysteresis depends on part number. See device selection table for details. VOV – 50 mV
Selected OV Hysteresis depends on part number. See device selection table for details.  VOV – 100 mV
VOV_ACC OV Detection Accuracy TA = 25℃
 		 –10 10 mV
OV Detection Accuracy 0℃ ≤ TA ≤ 60℃
 		 –20 20 mV
OV Detection Accuracy -40℃ ≤ TA ≤ 110℃
 		 –50 50 mV
UNDER VOLTAGE PROTECTION (UV)
VUV UV Detection Range 1.0 3.5 V
VUV_STEP UV Detection Steps 50 mV
VUV_HYS UV Detection Hysteresis Selected OV Hysteresis depends on part number. See device selection table for details.  VUV + 50 mV
Selected OV Hysteresis depends on part number. See device selection table for details.  VUV + 100 mV
VUV_ACC UV Detection Accuracy TA = 25℃ –30 30 mV
UV Detection Accuracy -40 ≤ TA ≤ 110℃ –50 50 mV
VUV_MIN UV Detection Disabled Threshold Vn - Vn-1 where n = 2 to 7 and V1 - VSS 450 500 550 mV
OVER TEMPERATURE PROTECTION (OT)
TOT OT Detection Range Available options: 62°C, 65°C, 70°C, 75°C, 80°C, 83°C 62.0 83.0 °C
ROT_EXT_NTC NTC OT Detection External Resistance 2850 Ω
2570
2195
1915
1651
1525
ROT_EXT_PTC PTC OT Detection External Resistance 111100 Ω
TOT_ACC (1) OT Detection Accuracy (NTC) –5 5 °C
TOT_HYS(2) OT Detection Hysteresis (NTC) –10 °C
4186 Ω
3530 Ω
RTC Internal Pull Up Resistor After TI Factory Trim 19.4 20 20.6 kΩ
UNDER TEMPERATURE PROTECTION (UT)
TUT UT Detection Threshold –30.0 0.0 °C
RUT_EXT_NTC NTC UT Detection External Resistance 111100 Ω
68900
42200
  26700
RUT_ACC UT Detection External Resistance Accuracy –2% 2%
TUT_HYS UT Detection Hysteresis (NTC) 10 °C
17800 Ω
TUT_ACC(1) UT Detection Accuracy (NTC) –5 5 °C
OPEN WIRE PROTECTION (OW)
VOW OW Detection Threshold Vn < Vn-1 where n = 2 to 7 –200 mV
V1 - VSS 500 mV
VOW_HYS OW Detection Hysteresis Vn < Vn-1 where n = 1 to 7 VOW +100 mV
VOW_ACC OW Detection Accuracy -40 ℃ ≤ TA ≤ 110℃ –25 25 mV
SUPPLY AND LEAKAGE CURRENT
ICC Supply Current No fault detected. 2 3.5 µA
ICC_FAULT Supply Current Fault detected, COUT active High 6V output, DOUT active low. Other faults 20 25 µA
ICC_FAULT Supply Current Fault detected, COUT active High 6V output, DOUT active low. UV fault only 3 5 µA
IIN(2) Input Current at Vx Pins Vn - Vn-1 and V1 - VSS = 4V, where n = 2 to 7, Open Wire Enabled  –0.3 0.3 µA
Vn - Vn-1 and V1 - VSS = 4V, where n = 2 to 7, Open Wire Disabled  –0.1 0.1 µA
OUTPUT DRIVE, COUT and DOUT, CMOS ACTIVE HIGH VERSIONS ONLY
VOUT_AH Output Drive Voltage for COUT and DOUT, Active High 6V Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 7, VDD = 25V, IOH = 100 µA measured out of COUT, DOUT pin. 6 V
Output Drive Voltage for COUT and DOUT, Active High VDD VDD - VCOUT or VDOUT, Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 7, IOH = 10 µA measured out of COUT, DOUT pin. 0 1 1.5 V
Output Drive Voltage for COUT and DOUT, Active High 6V VDD - VCOUT or VDOUT, If 6 of 7 cells are short circuited and only one cell remains powered and > VOV, VDD = Vx (cell voltage), IOH = 100 µA, 0 1 1.5 V
Output Drive Voltage for COUT and DOUT, Active High 6V and VDD Vn - Vn-1 and V1 - VSS < VOV, where n = 2 to 7, VDD = 25 V, IOH = 100 µA measured into pin 250 400 mV
ROUT_AH Internal Pull Up Resistor 80 100 120 kΩ
IOUT_AH_H OUT Source Current (during OV) Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 7, VDD = 25 V, OUT = 0V. Measured out of COUT, DOUT pin 6.5 mA
IOUT_AH_L OUT Sink Current (no OV) Vn - Vn-1 and V1 - VSS < VOV, where n = 2 to 7, VDD = 25 V, OUT = VDD. Measured into COUT, DOUT pin 0.3 3 mA
OUTPUT DRIVE, COUT and DOUT, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
VOUT_AL Output Drive Voltage for COUT and DOUT, Active Low Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 7, VDD = 25 V, IOH = 100 µA measured into COUT, DOUT pin. 250 400 mV
IOUT_AL_L OUT Source Current (during OV) Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 7, VDD = 25 V, OUT = VDD. Measured into COUT, DOUT pin. 0.3 3 mA
IOUT_AL_H OUT Sink Current (no OV) Vn - Vn-1 and V1 - VSS < VOV, where n = 2 to 7, VDD = 25 V, OUT = VDD. Measured out of COUT, DOUT pin. 100 nA
(1) Assured by design. This accuracy assumes the external resistance is within ±2% of the R_OT_EXT values for the corresponding temperature threshold.
(2) Assured by design