SLUSCM3K June   2016  – July 2020 BQ77904 , BQ77905

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Functionality Summary
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Protection Summary
      2. 8.3.2  Fault Operation
        1. 8.3.2.1  Operation in OV
        2. 8.3.2.2  Operation in UV
        3. 8.3.2.3  Operation in OW
        4. 8.3.2.4  Operation in OCD1
        5. 8.3.2.5  Operation in OCD2
        6. 8.3.2.6  Operation in SCD
        7. 8.3.2.7  Overcurrent Recovery Timer
        8. 8.3.2.8  Load Removal Detection
        9. 8.3.2.9  Load Removal Detection in UV
        10. 8.3.2.10 Operation in OTC
        11. 8.3.2.11 Operation in OTD
        12. 8.3.2.12 Operation in UTC
        13. 8.3.2.13 Operation in UTD
      3. 8.3.3  Protection Response and Recovery Summary
      4. 8.3.4  Configuration CRC Check and Comparator Built-In-Self-Test
      5. 8.3.5  Fault Detection Method
        1. 8.3.5.1 Filtered Fault Detection
      6. 8.3.6  State Comparator
      7. 8.3.7  DSG FET Driver Operation
      8. 8.3.8  CHG FET Driver Operation
      9. 8.3.9  External Override of CHG and DSG Drivers
      10. 8.3.10 Configuring 3-S, 4-S, or 5-S Mode
      11. 8.3.11 Stacking Implementations
      12. 8.3.12 Zero-Volt Battery Charging Inhibition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 FAULT Mode
        3. 8.4.1.3 SHUTDOWN Mode
        4. 8.4.1.4 Customer Fast Production Test Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 9.1.1.2 Protecting CHG and LD
        3. 9.1.1.3 Protecting CHG FET
        4. 9.1.1.4 Using Load Detect for UV Fault Recovery
        5. 9.1.1.5 Temperature Protection
        6. 9.1.1.6 Adding Filter to Sense Resistor
        7. 9.1.1.7 Using a State Comparator in an Application
          1. 9.1.1.7.1 Examples
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Example
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Protection Response and Recovery Summary

Table 8-3 summarizes how each fault condition affects the state of the DSG and CHG output signals, as well as the recovery conditions required to resume charging and/or discharging. As a rule, the CHG and DSG output drivers are enabled only when no respective fault conditions are present. When multiple simultaneous faults (such as an OV and OTD) are present, all faults must be cleared before the FET can resume operation.

Table 8-3 Fault Condition, State, and Recovery Methods
FAULTFAULT TRIGGER CONDITIONCHGDSGRECOVERY METHODTRIGGER DELAYRECOVERY DELAY
CTRC disabledCTRC disabled for deglitch delay timeOFF—CTRC must be enabled for deglitch delay timetCTRDEG_ONtCTRDEG_OFF
CTRD disabledCTRD disabled for deglitch delay time—OFFCTRD must be enabled for deglitch delay time
OVV(Cell) rises above VOV for delay timeOFF—V(Cell) drops below VOV – VHYS_OV for delaytOVn_DELAY
UVV(Cell) drops below VUV for delay time—OFFV(Cell) rises above VUV + VHYS_UV for delaytUVn_DELAY
OWVCX – VCX–1 < VOW for delay timeOFFOFFBad VCX recovers such that VCX – VCX–1 > VOW + VOW_HYS for delaytOWn_DELAY
OCD1, OCD2, SCD(VSRP - VSRN) < VOCD1, VOCD2, or VSCD for delay timeOFFOFFRecovery delay expires OR
LD detects < VLDT OR
Recovery delay expires + LD detects < VLDT		tOCD1_DELAY, tOCD2_DELAY, tSCD_DELAY,tCD_REC
OTC(1)Temperature rises above TOTC for delay timeOFF—Temp drops below TOTC – TOTC_REC for delaytOTC_DELAY
OTD(1)Temperature rises above TOTD for delay timeOFFOFFTemp drops below TOTD – TOTD_REC for delaytOTD_DELAY
UTC(1)Temperature drops below TUTC for delay timeOFF—Temperature rises above TUTC + TUTC_REC for delaytUTC_DELAY
UTD(1)Temp drops below TUTD for delay timeOFFOFFTemp rises above TUTD + TUTD_REC for delaytUTD_DELAY
(1) TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected thermistor resistance.

For BQ77904 and BQ77905 devices to prevent CHG FET damage, there are times when the CHG FET may be enabled even though an OV, UTC, OTC, or CTRC low event has occurred. See the State Comparator section for details.