SLUSCM3K June   2016  – July 2020 BQ77904 , BQ77905

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Functionality Summary
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Protection Summary
      2. 8.3.2  Fault Operation
        1. 8.3.2.1  Operation in OV
        2. 8.3.2.2  Operation in UV
        3. 8.3.2.3  Operation in OW
        4. 8.3.2.4  Operation in OCD1
        5. 8.3.2.5  Operation in OCD2
        6. 8.3.2.6  Operation in SCD
        7. 8.3.2.7  Overcurrent Recovery Timer
        8. 8.3.2.8  Load Removal Detection
        9. 8.3.2.9  Load Removal Detection in UV
        10. 8.3.2.10 Operation in OTC
        11. 8.3.2.11 Operation in OTD
        12. 8.3.2.12 Operation in UTC
        13. 8.3.2.13 Operation in UTD
      3. 8.3.3  Protection Response and Recovery Summary
      4. 8.3.4  Configuration CRC Check and Comparator Built-In-Self-Test
      5. 8.3.5  Fault Detection Method
        1. 8.3.5.1 Filtered Fault Detection
      6. 8.3.6  State Comparator
      7. 8.3.7  DSG FET Driver Operation
      8. 8.3.8  CHG FET Driver Operation
      9. 8.3.9  External Override of CHG and DSG Drivers
      10. 8.3.10 Configuring 3-S, 4-S, or 5-S Mode
      11. 8.3.11 Stacking Implementations
      12. 8.3.12 Zero-Volt Battery Charging Inhibition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 FAULT Mode
        3. 8.4.1.3 SHUTDOWN Mode
        4. 8.4.1.4 Customer Fast Production Test Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 9.1.1.2 Protecting CHG and LD
        3. 9.1.1.3 Protecting CHG FET
        4. 9.1.1.4 Using Load Detect for UV Fault Recovery
        5. 9.1.1.5 Temperature Protection
        6. 9.1.1.6 Adding Filter to Sense Resistor
        7. 9.1.1.7 Using a State Comparator in an Application
          1. 9.1.1.7.1 Examples
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Example
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.1.1.7.1 Examples

As an example, using a 5-Ah battery, with 1C-rate (5 A) charge and 2C-rate (10 A) discharge, the sense resistor is 3 mΩ or less. The typical current to turn on the FET body diode protection is 667 mA using this example. Because there is no built-in hysteresis, noise can reset the state comparator counter and toggle off the FET body diode protection and vice versa; thus, it is normal to observe the device toggles the FET body diode protection on or off within a 1-mV to 3-mV range. With a 3-mΩ sense resistor, it is about 330 mA to 1 A. As this behavior is due to noise from the system, the FET toggling behavior usually occurs right at the typical 2-mV state comparator threshold. As current increases or decreases from the typical value, the detection is more solid and has less frequent FET toggling. Using this example, either charge or discharge should provide a solid FET body diode protection detection.

Look at the device behavior during an OV event (and no other fault is detected). In an OV event, CHG FET is off and DSG FET is on. If a discharge of > –1 A occurs, the device would turn on the CHG FET immediately to allow the full discharge current to pass through. Once the overcharged cell is discharged to the OV recovery level, the OV fault is recovered and the CHG driver turns on (or remains on in this scenario) and the state comparator is turned off.

If the discharge current is < 1 A when the device is still in an OV fault, the CHG FET may toggle on and off until the overcharged cell voltage is reduced down to the OV recovery level. When the OV fault recovers, the CHG FET is solidly turned on and the state comparator is off.

Without the FET body diode protection, if a discharge occurs during an OV fault state, the discharge current can only pass through the CHG FET body diode until the OV fault is recovered. This increases the risk of damaging the CHG FET if the MOSFET is not rated to sustain this amount of current through its body diode. It also increases the FET temperature as current is now carried through the body diode.