SLUSCU0I March   2018  – September 2020 BQ77915


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Table
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1.  Operation in OV
        2.  Operation in UV
        3.  Operation in OW
        4.  Operation in OCD1
        5.  Operation in OCD2
        6.  Programming the OCD1/2 Delay Using the OCDP Pin
        7.  Operation in SCD
        8.  Operation in OCC
        9.  Overcurrent Recovery Timer
        10. Load Detection and Load Removal Detection
        11. Operation in OTC
        12. Operation in OTD
        13. Operation in UTC
        14. Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. Power On Reset (POR)
        2. NORMAL Mode
        3. FAULT Mode
        4. HIBERNATE Mode
        5. SHUTDOWN Mode
        6. Customer Fast Production Test Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. CHG and DSG FET Rise and Fall Time
        2. Protecting CHG and LD
        3. Protecting the CHG FET
        4. Using Load Detect for UV Fault Recovery
        5. Temperature Protection
        6. Adding RC Filters to the Sense Resistor
        7. Using the State Comparator in an Application
          1. Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Design Example
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Stacking Implementations

Higher than 5-series cell packs may be supported by daisy-chaining multiple devices. Each device ensures OV, UV, OW, OTC, OTD, UTC, and UTD protections of its directly monitored cells, while any fault conditions automatically disable the global CHG and/or DSG FET driver.


Upper devices do not provide OCC, OCD1, OCD2, or SCD protections, as these are based on pack current. For the BQ77915 device used on the upper stack, the SRP and SRN pins should be shorted to prevent false detection.

To configure higher-cell packs, follow this procedure:

  • Each device must have a connection on at least each of its three lowest cell input pins.
  • It is highly recommended to connect higher cell count to the upper devices (for example, for a 7-series configuration, connect four cells on the upper device and three cells on the bottom device). This is to provide stronger CTRx signal to the bottom device.
  • Ensure that each device’s CCFG pin is configured appropriately for its specific number of cells (that is, three, four, or five cells).
  • Connect the upper CHG pins with an RCTRx to the immediate lower device CTRC pin.
  • Connect the upper DSG pins with an RCTRx to the immediate lower device CTRD pin.
  • All upper devices should have their SRP and SRN pins shorted to their VSS pins.
  • Connect the upper CBI pins with an RCB to the immediate lower device CBO pin.
  • Connect the upper LPWR pins with an RHIB to the immediate lower device PRES pin.
  • Connect the upper OCDP pins with a 10-MΩ resistor to VSS. Use the lower OCDP pin to program the OCD1/2 delay.
GUID-49B698AE-FF4B-46B7-BD04-6BF7ED02269A-low.gifFigure 9-14 10-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled