SLUSCU0I March 2018 – September 2020 BQ77915
The DSG pin is driven high only when no related faults (UV, OW, OTD, UTD, OCD1, OCD2, SCD, OCC, and CTRD disabled) are present and the device is not in HIBERNATE mode of operation. It is a fast switching driver with a target on resistance of about 15 Ω–20 Ω and an off resistance of RDSGOFF. It is designed to enable customers to select the optimized RGS value to archive the desirable FET rise and fall time per the application requirement and the choice of FET characteristics. When the DSG FET is turned off, the DSG pin drives low and all discharge overcurrent protections (OCD1, OCD2, SCD) are disabled to better conserve power. These resume operation when the DSG FET is turned on. The device provides FET body diode protection through the state comparator if one FET driver is on and the other FET driver is off.
The DSG driver may be turned on to prevent FET damage if the battery pack is charging while a discharge inhibit fault condition is present. This is done by the state comparator. The state comparator (with VSTATE_C threshold and VSTATE_C_HYS hysteresis) remains on for the entire duration of a DSG fault with no CHG fault event.
See the Section 9.3.8 section for details.
The presence of any related faults, as shown in Figure 9-8, results in the DSGFET_OFF signal.