SLUSCU0I March   2018  – September 2020 BQ77915

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Table
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

NUMBERNAMEI/ODESCRIPTION
1VDDP(1)Supply voltage
2AVDDOAnalog supply (only connect to a capacitor)
3VC5ICell voltage sense inputs
4VC4I
5VC3I
6VC2I
7VC1I
8VC0I
9VSSPAnalog ground
10SRPICurrent sense input connecting to the battery side of the sense resistor
11SRNICurrent sense input connecting to the pack side of the sense resistor
12DSGODSG FET driver output
13CHGOCHG FET driver output
14LDIPACK– load removal detection
15LPWROHIBERNATE mode communication pin. Connect to the PRES pin of the lower device in a stack configuration. For a single device, leave the LPWR pin floating.
16CBIICell balancing input. Leave the CBI pin floating to disable cell balancing, and do not drive with an external supply. Drive the pin low to enable cell balancing. In a stacked configuration, connect the CBI pin of an upper device to the CBO pin of the immediate lower device.
17OCDPIConnecting a resistor from this pin to VSS programs the OCD1/2 fault detection delay. Connect to a 10-MΩ resistor to VSS for the upper devices in a stack.
18TSIThermistor measurement input. Connect a 10-kΩ resistor to the VSS pin if the function is not used.
19VTBOThermistor bias output
20CCFGICell in-series configuration input
21CBOOCell balancing output. Connect through a 10-k resistor to the CBI pin of the upper device in a stacked configuration. For a single device, leave the CBO pin floating.
22PRESIHIBERNATE mode input. Drive high for NORMAL mode operation. Leave the PRES pin floating for HIBERNATE mode. Connect to the LPWR pin of the upper device in a stack configuration.
23CTRCICHG and DSG override inputs
24CTRDI
I = Input, O = Output, P = Power