SLUSDQ4 April 2019 BQ79606A-Q1
CVDD is the supply input for the daisy chain transceiver circuits. CVDD receives it's power externally from VLDO. This allows for external filtering for noisy applications. CVDD is monitored for under-voltage constantly. If VCVDD < VCVDDUV the RAIL_FAULT[CVDDUV] bit is set. Additionally, the CVSS pin is monitored continuously, and the SYS_FAULT2[CVSS_OPEN] bit is set if an 'open' condition is detected for CVSS.
VIO is the supply for digital inputs. The RX, WAKEUP (for base) and NFAULT (if used) pins are all referenced to VIO (TX must be pulled high at host side). VIO is supplied from the system logic supply, or is connected to VLDO or CVDD for stack devices (for systems without a logic supply). VIO is monitored for under-voltage constantly. If VVIO < VVIOUV the SYS_FAULT3[VIOUV] bit is set. Do not toggle VIO in shut down mode, otherwise a device could exit shutdown mode.