SLUSDQ4 April 2019 BQ79606A-Q1
Due to the one time programming limitation of OTP NVM, two unused pages of OTP memory are available for the end customer to program. The status of the pages is held in the OTP_CUST1_STAT* and OTP_CUST2_STAT* registers. The OTP_CUST1_STAT1 and OTP_CUST2_STAT1 registers provide information on the current status of the page including the load status (if loaded, if loaded with error, if load failed), whether the page has been programmed successfully and is able to be loaded, or if the page is available for burning. OTP_CUST1_STAT2 and OTP_CUST2_STAT2 registers provide the programmed status.
When a reset occurs, the BQ79606A-Q1 evaluates the OTP page status and chooses the latest, valid OTP page to load. Page 2 has priority over page 1. If both pages have not been written, the factory OTP defaults (as indicated in the summary register table) are loaded. A valid page is one where the OTP_CUST*_STAT1[PROGOK] bit is '1'. When the page is selected for loading, the OTP_CUST*_STAT1[LOADED] bit is set. If a single error occurs in the loading of the page, the page is loaded after the single error is corrected and the OTP_CUST*_STAT1[LOADWRN] bit is set. Additionally, the SEC_BLK register is updated with the location of the error corrected block. If a double error occurs, the loading of that block is terminated and the hardware defaults of that block are loaded (as indicated in the summary register table). The overall page loading process is not terminated for a DED, only the affected block is terminated. When a DED occurs, the OTP_CUST*_STAT1[LOADERR] bit is set. Additionally, the DED_BLK register is updated with the block where the double error occurred. See the Error Check and Correct (ECC) OTP section for more details on error correction.