SBOS571C August   2011  – August 2018 BUF20800-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 General-call Reset and Power-up
      2. 7.3.2 Output Voltage
      3. 7.3.3 Output Latch
      4. 7.3.4 Programmable VCOM
      5. 7.3.5 REFH and REFL Input range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Replacement of Traditional Gamma Buffer
      2. 7.4.2 Dynamic Gamma Control
    5. 7.5 Programming
      1. 7.5.1 Two-wire Bus Overview
      2. 7.5.2 Data Rates
      3. 7.5.3 Read/Write Operations
        1. Writing
        2. Reading
      4. 7.5.4 Register Maps
        1. Addressing the BUF20800-Q1
      5. 7.5.5 Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Capacitor Selection
        2. REFH and REFL Voltage Settings
      3. 8.2.3 Application Curves
      4. 8.2.4 Configuration for 20 Gamma Channels
      5. 8.2.5 Configuration for 22 Gamma Channels
      6. 8.2.6 The BUF20800-Q1 in Industrial Applications
      7. 8.2.7 Total TI Panel Solution
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PowerPAD Design Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

General PowerPAD Design Considerations

The BUF20800-Q1 is available in a thermally-enhanced PowerPAD package. This package is constructed using a downset leadframe upon which the die is mounted, see Figure 21(a) and Figure 21(b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 21(c). This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing a good thermal path away from the thermal pad.

BUF20800-Q1 appinfo_pkgviews_bos571.gifFigure 21. Views of Thermally-Enhanced DCP Package

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have low power dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB.

The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD.

  1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the thermal pad.
  2. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns for the HTSSOP-38 DCP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package (SLMA002), available for download at These holes should be 13 mils in diameter. Keep them small, so that solder wicking through the holes is not a problem during reflow. An example thermal land pattern mechanical drawing is attached to the end of this data sheet.
  3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the BUF20800-Q1 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered; thus, wicking is not a problem.
  4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins.
  5. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the BUF20800-Q1 PowerPAD package should make their connection to the internal plane with a complete connection around the entire circumference of the plated-through hole.
  6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its twelve holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking prevents solder from being pulled away from the thermal pad area during the reflow process.
  7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
  8. With these preparatory steps in place, the BUF20800-Q1 IC is simply placed in position and run through the solder reflow operation as any standard surface mount component. This preparation results in a properly installed part.

For a given θJA (listed in the Electrical Characteristics table), the maximum power dissipation is shown in Figure 22, and is calculated by Equation 3:

Equation 3. BUF20800-Q1 q_pd_bos399.gif


  • PD = maximum power dissipation (W)
  • TMAX = absolute maximum junction temperature
  • TA = free-ambient air temperature (°C)
BUF20800-Q1 appinfo_maxpwrdiss_ta_bos571.gifFigure 22. Maximum Power Dissipation
vs Free-Air Temperature
(with PowerPAD soldered down)