SWRS109C May   2011  – December 2016 CC110L

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
      1. 4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz
      2. 4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz
    6. 4.6  Typical RX Current Consumption Over Temperature and Input Power Level, 868 or 915 MHz
    7. 4.7  RF Receive Section
      1. 4.7.1 Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting
      2. 4.7.2 Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting
      3. 4.7.3 Blocking and Selectivity
    8. 4.8  RF Transmit Section
      1. 4.8.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
      2. 4.8.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
    9. 4.9  Crystal Oscillator
    10. 4.10 Frequency Synthesizer Characteristics
    11. 4.11 DC Characteristics
    12. 4.12 Power-On Reset
    13. 4.13 Thermal Characteristics
    14. 4.14 Typical Characteristics
      1. 4.14.1 Typical Characteristics, RX Current Consumption
      2. 4.14.2 Typical Characteristics, Blocking and Selectivity
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
    6. 5.6  Chip Status Byte
    7. 5.7  Register Access
    8. 5.8  SPI Read
    9. 5.9  Command Strobes
    10. 5.10 FIFO Access
    11. 5.11 PATABLE Access
    12. 5.12 Microcontroller Interface and Pin Configuration
      1. 5.12.1 Configuration Interface
      2. 5.12.2 General Control and Status Pins
    13. 5.13 Data Rate Programming
    14. 5.14 Receiver Channel Filter Bandwidth
    15. 5.15 Demodulator, Symbol Synchronizer, and Data Decision
      1. 5.15.1 Frequency Offset Compensation
      2. 5.15.2 Bit Synchronization
      3. 5.15.3 Byte Synchronization
    16. 5.16 Packet Handling Hardware Support
      1. 5.16.1 Packet Format
        1. 5.16.1.1 Arbitrary Length Field Configuration
        2. 5.16.1.2 Packet Length > 255
      2. 5.16.2 Packet Filtering in Receive Mode
        1. 5.16.2.1 Address Filtering
        2. 5.16.2.2 Maximum Length Filtering
        3. 5.16.2.3 CRC Filtering
      3. 5.16.3 Packet Handling in Transmit Mode
      4. 5.16.4 Packet Handling in Receive Mode
      5. 5.16.5 Packet Handling in Firmware
    17. 5.17 Modulation Formats
      1. 5.17.1 Frequency Shift Keying
      2. 5.17.2 Amplitude Modulation
    18. 5.18 Received Signal Qualifiers and RSSI
      1. 5.18.1 Sync Word Qualifier
      2. 5.18.2 RSSI
      3. 5.18.3 Carrier Sense (CS)
        1. 5.18.3.1 CS Absolute Threshold
        2. 5.18.3.2 CS Relative Threshold
      4. 5.18.4 Clear Channel Assessment (CCA)
    19. 5.19 Radio Control
      1. 5.19.1 Power-On Start-Up Sequence
        1. 5.19.1.1 Automatic POR
        2. 5.19.1.2 Manual Reset
      2. 5.19.2 Crystal Control
      3. 5.19.3 Voltage Regulator Control
      4. 5.19.4 Active Modes (RX and TX)
      5. 5.19.5 RX Termination
      6. 5.19.6 Timing
        1. 5.19.6.1 Overall State Transition Times
        2. 5.19.6.2 Frequency Synthesizer Calibration Time
    20. 5.20 Data FIFO
    21. 5.21 Frequency Programming
    22. 5.22 VCO
      1. 5.22.1 VCO and PLL Self-Calibration
    23. 5.23 Voltage Regulators
    24. 5.24 Output Power Programming
    25. 5.25 General Purpose and Test Output Control Pins
    26. 5.26 Asynchronous and Synchronous Serial Operation
      1. 5.26.1 Asynchronous Serial Operation
      2. 5.26.2 Synchronous Serial Operation
    27. 5.27 System Considerations and Guidelines
      1. 5.27.1 SRD Regulations
      2. 5.27.2 Frequency Hopping and Multi-Channel Systems
      3. 5.27.3 Wideband Modulation when not Using Spread Spectrum
      4. 5.27.4 Data Burst Transmissions
      5. 5.27.5 Continuous Transmissions
      6. 5.27.6 Increasing Range
    28. 5.28 Configuration Registers
      1. 5.28.1 Configuration Register Details - Registers with preserved values in SLEEP state
      2. 5.28.2 Configuration Register Details - Registers that Loose Programming in SLEEP State
      3. 5.28.3 Status Register Details
    29. 5.29 Development Kit Ordering Information
  6. 6Applications, Implementation, and Layout
    1. 6.1 Bias Resistor
    2. 6.2 Balun and RF Matching
    3. 6.3 Crystal
    4. 6.4 Reference Signal
    5. 6.5 Additional Filtering
    6. 6.6 Power Supply Decoupling
    7. 6.7 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation from Texas Instruments
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
    7. 7.7 Additional Acronyms
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configuration and Functions

3.1 Pin Diagram

The CC110L pinout is shown in Figure 3-1 and Table 3-1. See Section 5.25 for details on the I/O configuration.

CC110L po_top_view_swrs109.gif Figure 3-1 Pinout Top View

3.2 Signal Descriptions

Table 3-1 Signal Descriptions

Pin No. Pin Name Pin Type Description
1 SCLK Digital Input Serial configuration interface, clock input
2 SO (GDO1) Digital Output Serial configuration interface, data output
Optional general output pin when CSn is high
3 GDO2 Digital Output Digital output pin for general use:
  • Test signals
  • FIFO status signals
  • Clear channel indicator
  • Clock output, down-divided from XOSC
  • Serial output RX data
4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O's and for the digital core voltage regulator
5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling

NOTE: This pin is intended for use with the CC110L only. It can not be used to provide supply voltage to other devices
6 GDO0 Digital I/O Digital output pin for general use:
  • Test signals
  • FIFO status signals
  • Clear channel indicator
  • Clock output, down-divided from XOSC
  • Serial output RX data
  • Serial input TX data
7 CSn Digital Input Serial configuration interface, chip select
8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input
9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
10 XOSC_Q2 Analog I/O Crystal oscillator pin 2
11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
12 RF_P RF I/O Positive RF input signal to LNA in receive mode
Positive RF output signal from PA in transmit mode
13 RF_N RF I/O Negative RF input signal to LNA in receive mode
Negative RF output signal from PA in transmit mode
14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
16 GND Ground (Analog) Analog ground connection
17 RBIAS Analog I/O External bias resistor for reference current
18 DGUARD Power (Digital) Power supply connection for digital noise isolation
19 GND Ground (Digital) Ground connection for digital noise isolation
20 SI Digital Input Serial configuration interface, data input