SCHS047I August   1998  – September 2017 CD4051B , CD4052B , CD4053B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Functional Diagrams of CD405xB
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions CD4051B
    2.     Pin Functions CD4052B
    3.     Pin Functions CD4053B
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted)(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIS (V) VEE (V) VSS (V) VDD (V) TEMP
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
Quiescent Device Current, IDD Max 5 –55°C 5 µA
–40°C 5
25°C 0.04 5
85°C 150
125°C 150
10 –55°C 10
–40°C 10
25°C 0.04 10
85°C 300
125°C 300
15 –55°C 20
–40°C 20
25°C 0.04 20
85°C 600
125°C 600
20 –55°C 100
–40°C 100
25°C 0.08 100
85°C 3000
125°C 3000
Drain to Source ON Resistance rON Max
0 ≤ VIS ≤ VDD
0 0 5 –55°C 800
–40°C 850
25°C 470 1050
85°C 1200
125°C 1300
0 0 10 –55°C 310
–40°C 300
25°C 180 400
85°C 520
125°C 550
0 0 15 –55°C 200
–40°C 210
25°C 125 240
85°C 300
125°C 300
Change in ON Resistance
(Between Any Two Channels),
∆rON
0 0 5 25°C 15
0 0 10 10
0 0 15 5
OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max) 0 0 18 –55°C ± 100 nA
–40°C
25°C ± 0.01 ± 100(2)
85°C ± 1000(2)
125°C
ON Channel Leakage Current: Any Channel ON (Max) or ALL Channels ON (Common OUT/IN) (Max) 5 or 0 -5 0 10.5 85°C ± 300(3) nA
5 0 0 18 85°C ± 300(3)
Capacitance Input, CIS –5 –5 –5 25°C 5 pF
Output, COS CD4051 25°C 30
CD4052 18
CD4053 9
Feed through, CIOS 0.2
Propagation Delay Time (Signal Input to Output) VDD
CD4051B CD4052B CD4053B Signal_Symbol_EC_table_CD4052B.gif
RL = 200 kΩ , 5 25°C 30 60 ns
CL = 50 pF, 10 15 30
tr , tf = 20 ns 15 10 20
CONTROL (ADDRESS OR INHIBIT), VC
Input Low Voltage, VIL , Max VIL = VDD
through 1 kΩ ;
VIH = VDD
through 1 kΩ
VEE = VSS,
RL = 1 kΩ to VSS,
IIS < 2 µA on All OFF Channels
5 –55°C 1.5 V
–40°C 1.5
25°C 1.5
85°C 1.5
125°C 1.5
10 –55°C 3
–40°C 3
25°C 3
85°C 3
125°C 3
15 –55°C 4
–40°C 4
25°C 4
85°C 4
125°C 4
Input High Voltage, VIH , Min 5 –55°C 3.5 V
–40°C 3.5
25°C 3.5
85°C 3.5
125°C 3.5
10 –55°C 7
–40°C 7
25°C 7
85°C 7
125°C 7
15 –55°C 11
–40°C 11
25°C 11
85°C 11
125°C 11
Input Current, IIN (Max) VIN = 0, 18 18 –55°C ± 0.1 µA
–40°C ± 0.1
25°C ± 10–5 ± 0.1
85°C ± 1
125°C ± 1
Propagation Delay Time Address-to-Signal OUT (Channels ON or OFF) (See Figure 10, Figure 11, and Figure 15) tr , tf = 20 ns,
CL = 50 pF,
RL = 10 kΩ
0 0 5 450 720 ns
0 0 10 160 320
0 0 15 120 240
–5 0 5 225 450
Propagation Delay Time Inhibit-to-Signal OUT (Channel Turning ON) (See Figure 11) tr , tf = 20 ns,
CL = 50 pF,
RL = 1 kΩ
0 0 5 400 720 ns
0 0 10 160 320
0 0 15 120 240
–10 0 5 200 400
Propagation Delay Time Inhibit-to-Signal OUT (Channel Turning OFF) (See Figure 17) tr , tf = 20 ns,
CL = 50 pF,
RL = 10 kΩ
0 0 5 200 450 ns
0 0 10 90 210
0 0 15 70 160
–10 0 5 130 300
Input Capacitance, CIN (Any Address or Inhibit Input) 5 7.5 pF
Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.
Determined by minimum feasible leakage measurement for automatic testing.
Does not apply to Hi-Rel CD4051BF and CD4051BFA3 devices.