SCHS047I August   1998  – September 2017 CD4051B , CD4052B , CD4053B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Functional Diagrams of CD405xB
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions CD4051B
    2.     Pin Functions CD4052B
    3.     Pin Functions CD4053B
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Parameter Measurement Information

CD4051B CD4052B CD4053B TCW_1_CD4052B.gifFigure 9. Typical Bias Voltages

NOTE

The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.

CD4051B CD4052B CD4053B TCW_2_CD4052B.gifFigure 10. Waveforms, Channel Being Turned ON (RL = 1 kΩ)
CD4051B CD4052B CD4053B TCW_3_CD4052B.gifFigure 11. Waveforms, Channel Being Turned OFF (RL = 1 kΩ)
CD4051B CD4052B CD4053B Figure_17.gifFigure 12. OFF Channel Leakage Current - Any Channel OFF
CD4051B CD4052B CD4053B On_State_circuit.gifFigure 13. On Channel Leakage Current - Any Channel On
CD4051B CD4052B CD4053B TCW_5_CD4052B.gifFigure 14. OFF Channel Leakage Current - All Channels OFF
CD4051B CD4052B CD4053B TWC_6_CD4052B.gifFigure 15. Propagation Delay - Address Input to Signal Output
CD4051B CD4052B CD4053B TWC_7_CD4052B.gifFigure 16. Propagation Delay - Inhibit Input to Signal Output
CD4051B CD4052B CD4053B TWC_8_CD4052B.gifFigure 17. Input Voltage Test Circuits (Noise Immunity)
CD4051B CD4052B CD4053B TWC_9_CD4052B.gifFigure 18. Quiescent Device Current
CD4051B CD4052B CD4053B TWC_10_CD4052B.gifFigure 19. Channel ON Resistance Measurement Circuit
CD4051B CD4052B CD4053B TWC_11_CD4052B.gifFigure 20. Input Current
CD4051B CD4052B CD4053B TWC_12_CD4052B.gifFigure 21. Feedthrough (All Types)
CD4051B CD4052B CD4053B TWC_13_CD4052B.gifFigure 22. Crosstalk Between Any Two Channels (All Types)
CD4051B CD4052B CD4053B TWC_14_CD4052B.gifFigure 23. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
CD4051B CD4052B CD4053B TWC_15_CD4052B.gif
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.
Figure 24. Typical Time-Division Application of the CD4052B
CD4051B CD4052B CD4053B TWC_16_CD4052B.gifFigure 25. 24-to-1 MUX Addressing