SCES945 May   2022 CDCBT1001

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Down Tolerant Input
      2. 7.3.2 Up Conversion
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Processor Clock Up Translation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY CHARACTERISTICS
IDD_IN Current consumption on VDD_IN Both input and output clocks are toggling. 2 pF load termination. f0 = 12 MHz. 35 µA
Both input and output clocks are toggling. 2 pF load termination. f0 = 24 MHz. 60 µA
IDD_OUT Current consumption on VDD_OUT Both input and output clocks are toggling. 2 pF load termination. f0 = 12 MHz. 500 µA
Both input and output clocks are toggling. 2 pF load termination. f0 = 24 MHz. 1000 µA
CLOCK INPUT CHARACTERISTICS
f0 Operating frequency DC 24 MHz
IIN_LEAK Input leakage current –8 8 µA
VIH Input voltage high VDD_IN x 0.8 V
VIL Input voltage low VDD_IN x 0.2 V
∆v/∆t Input edge rate 0.01 V/ns
CI Input capacitance 2 pF
tstartup Time after power supply exceeds 0.5 V before applying input clock, to ensure glitchless output 225 us
CLOCK OUTPUT CHARACTERISTICS
VOH Output voltage high VI = VIH, IOH = -100 µA, VDD_OUT = 1.62-1.98 V VDD_OUT – 0.1 V
VOH Output voltage high VI = VIH, IOH = -8 mA, VDD_OUT = 1.62 V 1.2 V
VOL Output voltage low VI = VIL, IOL = 100 µA, VDD_OUT = 1.62-1.98 V 0.1 V
VOL Output voltage low VI = VIL, IOL = 8 mA, VDD_OUT = 1.62 V 0.45 V
ODC Output duty cycle Input duty cycle = 45% - 55%, input slew rate ≥ 0.2 V/ns, VIL ≤ 0.15 * VDD_IN, VIH ≥ 0.85 * VDD_IN, VIH - VIL ≥ 850 mVpp 40 60 %
Input duty cycle = 45% - 55%, input slew rate ≥ 0.2 V/ns, VIL ≤ 0.2 * VDD_IN, VIH ≥ 0.8 * VDD_IN, VIH - VIL ≥ 850 mVpp 37 63 %
tR, tF Clock output rise/fall time 20% to 80%, 2 pF load capacitance 3 ns
tPD Input-to-output propagation delay Input slew rate ≥ 0.2 V/ns, VIL ≤ 0.2 * VDD_IN, VIH ≥ 0.8 * VDD_IN, VIH - VIL ≥ 850 mVpp 10 ns
Rout Output impedance 34 Ω
CLOCK OUTPUT PERFORMANCE
RJRMS-ADD 12 kHz to 5 MHz additive RMS random jitter f0 =24 MHz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp 0.8 ps
PN10 Output phase noise @10 Hz f0 =24 MHz, input phase noise = -104 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –100 dBc/Hz
PN100 Output phase noise @100 Hz f0 =24 MHz, input phase noise = -127 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –110 dBc/Hz
PN1k Output phase noise @1 kHz f0 =24 MHz, input phase noise = -137 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –120 dBc/Hz
PN10k Output phase noise @10 kHz f0 =24 MHz, input phase noise = -159 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –130 dBc/Hz
PN100k Output phase noise @100 kHz f0 =24 MHz, input phase noise = -164 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –140 dBc/Hz
PN1M Output phase noise @1 MHz f0 =24 MHz, input phase noise = -166 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –148 dBc/Hz
PN5M Output phase noise @5 MHz f0 =24 MHz, input phase noise = -165 dBc/Hz, input slew rate ≥ 0.2 V/ns, VIH - VIL ≥ 850 mVpp –148 dBc/Hz