SNAS811 July 2020 – May CDCE6214
The energy of the harmonics from the rectangular clock signal can be spread over a certain frequency range. This frequency deviation leads to lowered average amplitude of the harmonics. This can help to mitigate electromagnetic interference (EMI) challenges in a system when the receiver supports this mode of operation. The modulation shape is triangular.
The SSC clock is generated through the fractional-N PLL. When SSC is enabled, SSC clock is available on all clock sourced from the PLL. Reference clock or PFD clock is available on the OUT1–OUT4 pins.
Down spread and center spread are supported. The following modes are supported.
Using these pre-configured settings, fmod of 31.5 kHz is synthesized for 100-MHz output clock.
|R41 - SSC_EN||R42 - SSC_TYPE||R42[3:1] - SSC_SEL||DESCRIPTION|
|0h||X||X||No SSC modulation at output|
|1h||0h||X||Down spread SSC modulation. SSC spread is determined by ssc_sel|
|1h||1h||X||Center spread SSC modulation. SSC spread is determined by ssc_sel|
|1h||X||0h||25-MHz PFD, +/- 0.25% for Center spread, -0.25% for Down spread.|
|1h||X||1h||25-MHz PFD, +/- 0.50% for Center spread, -0.50% for Down spread.|
|1h||X||2h||50-MHz PFD, +/- 0.25% for Center spread, -0.25% for Down spread.|
|1h||X||3h||50-MHz PFD, +/- 0.50% for Center spread, -0.50% for Down spread.|
|1h||X||4h-7h||Do not use|
|NO.||CLASS||DATA RATE||ARCHITECTURE||MEASURED PNA METHOD||MEASURED SCOPE METHOD||SPEC LIMIT||RESULT|
|1||Gen4||16 Gb/s||CC||195 fs||260 fs||500 fs||PASS|
|2||Gen4||16 Gb/s||SRIS||-||490 fs||500 fs||PASS|
|3||Gen5||32 Gb/s||CC||87 fs||111 fs||150 fs||PASS|
|4||Gen5||32 Gb/s||SRIS||-||157 fs||*||*|