SCAS886E August   2009  – December 2015 CDCLVP1212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: LVCMOS Input
    6. 7.6  Electrical Characteristics: Differential Input
    7. 7.7  Electrical Characteristics: LVPECL Output, At VCC = 2.375 V to 2.625 V
    8. 7.8  Electrical Characteristics: LVPECL Output, at VCC = 3.0 V to 3.6 V
    9. 7.9  Pin Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVPECL Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Fanout Buffer for Line Card Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 2:12 Differential Buffer
  • Selectable Clock Inputs Through Control Terminal
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
  • 12 LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 88 mA
  • Very Low Additive Jitter: <100 fs, rms in 10-kHz to 20-MHz Offset Range:
    • 57 fs, rms (typ) @ 122.88 MHz
    • 48 fs, rms (typ) @ 156.25 MHz
    • 30 fs, rms (typ) @ 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 550 ps
  • Maximum Output Skew: 25 ps
  • LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • ESD Protection Exceeds 2 kV (HBM)
  • Supports 105°C PCB Temperature (Measured with a Thermal Pad)
  • Available in 6-mm × 6-mm QFN-40 (RHA) Package

2 Applications

  • Wireless Communications
  • Telecommunications/Networking
  • Medical Imaging
  • Test and Measurement Equipment

3 Description

The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1212 is packaged in a small 40-terminal, 6-mm x 6-mm QFN package and is characterized for operation from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCLVP1212 QFN (40) 6.00 mm x 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

3.0.0.1 Functional Block Diagram

CDCLVP1212 fbd_cas886.gif

Peak-to-Peak Voltage vs. Frequency

CDCLVP1212 tc_fqcy_diff_vout_swing02_cas877.gif