SCAS928D May   2012  – April 2019 CDCUN1208LP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Pin Configuration Overview
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1.1 Device Registers: Register 00-07

Register 00: OUT1
Register 01: OUT2
Register 02: OUT3
Register 03: OUT4
Register 04: OUT5
Register 05: OUT6
Register 06: OUT7
Register 07: OUT8

Table 11. CDCUN1208LP Register 0–7 Bit Definitions

RAM BIT BIT NAME RELATED BLOCK DESCRIPTION / FUNCTION POWER UP CONDITION
15 TI RESERVED TI RESERVED
14
13
12
11
10 OUTx_CMOS_MODE Reg 00: OUT1
Reg 01: OUT2
Reg 02: OUT3
Reg 03: OUT4
Reg 04: OUT5
Reg 05: OUT6
Reg 06: OUT7
Reg 07: OUT8		 OUTx CMOS MODE
1 – Both sides pseudo differential
0 – Both sides in phase		 0
9 OUTx_ERC[2:0] OUTx Edge Rate Control
111 – Medium
100 - Fast
000 - Slow		 0
8 0
7 0
6 TI RESERVED TI RESERVED 0
5 0
4 OUTx_OE[1:0] OUTx Output Enable
OTTP = LVCMOS
11 – OUT1P: ON | OUT1N: ON
10 – OUT1P: ON |OUT1N: OFF
01 – OUT1P: OFF| OUT1N: ON
00 – OUT1P: OFF| OUT1N: OFF
0
3 OTTP = Differential (LVDS, HCSL)
0
00 – OFF
11 - ON
2 OUTx_OTTP[1:0] OUTx Output Type
11 – HCSL
10 – Reserved
01 – LVCMOS
00 - LVDS		 0
1 0
0 OUTx_PD OUTx Buffer
1 – Disabled in Tri-State
0 - Enabled		 0

Table 12. CDCUN1208LP Registers 11–15 Bit Definitions

REGISTER ADDRESS RAM BIT BIT NAME RELATED BLOCK DESCRIPTION / FUNCTION POWER UP CONDITION
11 15 TI RESERVED
14 TI RESERVED
13 TI RESERVED
12 TI RESERVED
11 TI RESERVED
10 TI RESERVED
9 TI RESERVED
8 TI RESERVED 0
7 TI RESERVED 0
6 TI RESERVED 0
5 IN_DIV[1] Input
(IN2 – Divider)		 Input Divider Control
1 1 = /8
1 0 = /4
0 1 = /2
0 0 = /1		 0
4 IN_DIV[0] 0
3 IN_TYPE[1] Input(1)
(IN1 and IN2 Type)		 Input Type
1 1 = HCSL
1 0 = LVCMOS
0 1 = LVCMOS
0 0 = LVDS		 0
2 IN_TYPE[0] 0
1 INSEL[1] Input
(multiplexer)		 Input Multiplexer Control
1 1 = Control through INSEL pin
1 0 = Smart MUX enabled, IN 1=primary
0 1 = IN2 buffer selected
0 0 = IN1 buffer selected		 0
0 INSEL[0] 0
12-14 ALL TI RESERVED
15 2-15 TI RESERVED
1 RESET Device Reset
1 = Reset device
0 = Run device		 0
0 PD Device Power Down
1 = Device is powered down
0 = Device is active		 0
(1) When configuring device inputs as LVCMOS, apply the single-ended clock signal to INxP and leave INxN either floating or ground it. The power supply voltage (1.8 V, 2.5 V, or 3.3 V) applied to VDD (pin 5) establishes the switching thresholds for IN1 and IN2 in LVCMOS mode.