4 Revision History
Changes from C Revision (March 2017) to D Revision
- Changed applications listGo
- Added type descriptions to the Pin Functions tableGo
- Changed input voltage maximum from: VDDx + 0.5 to: VDD + 0.5 in the Absolute Maximum Ratings tableGo
- Added the junction temperature range to the Absolute Maximum Ratings tableGo
- Changed the output current unit from mA °C to mA and moved the °C unit to the storage temperature parameter in the Absolute Maximum Ratings tableGo
- Added note on VDD and VDDOx supply voltagesGo
- Added text "Pull ADDR to GND for I2C communication" to the CDCUN1208LP Host Configuration Pins tableGo
- Changed SPI Message Format graphic to correct SCS timing.Go
- Changed CDCUN1208LP Device Addressing - SPI Mode graphic to correct SCS timing.Go
- Changed SPI Timing Diagram graphic to correct SDI.Go
- Changed t3 in SPI Timing Specifications table to "SDI to SCL hold time"Go
- Changed t8 in SPI Timing Specifications table to "SCL falling edge to SCS release time"Go
- Changed I2C address to 7b'0101000 in CDCUN1208LP I2C Message - Addressing graphicGo
- Changed description to reflect that the I2C address is 7b'0101000 in CDCUN1208LP Device Addressing (I2C Address) sectionGo
- Added content to the Application Information section Go
Changes from B Revision (July 2013) to C Revision
- Changed Added Device Information Table, ESD Ratings tableApplication and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information .Go
- Added ΔV/ΔT2 to the Recommended Operating Conditions table.Go
- Added text "note that CDCUN1208LP supports only single-device" to the first paragraph of SPI Communication.Go
- Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in single-slave SPI configuration." to Writing to the CDCUN1208LP.Go
- Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in single-slave SPI configuration." to Reading From the CDCUN1208LP.Go
Changes from A Revision (January 2013) to B Revision
- Added slew rate note to Recommended Operating Conditions.Go
- Changed VIOPEN1.8 from 0.9 V to 0.75 V in Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, DIVIDE (SDA/MOSI), ERC(ADDR/CS), Mode.Go
- Changed Fast to Medium and Medium to Fast in Figure 28.Go
Changes from * Revision (May 2012) to A Revision
- Added Feature:160 fs RMS (10kHz-20MHz), HCSL at 100MHz.Go
- Added Features: Support PCIE gen1, gen2, gen3.Go
- Added text to the Description: "The clock buffer supports PCIE gen1, gen2 and gen3."Go
- Added text to the Clock Output Buffer Characteristics table: "Supporting PCIe gen1, gen2, gen3."Go
- Changed Table 4 From: DISABLED To: DISABLED in Tri_StateGo
- Changed Table 11 From: Disabled To: Disabled in Tri_State for OUTx_PD. Go
- Added text and Figure 41 to the PCI Express Applications section. Go