SCAS928D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
To initiate a SPI data transfer, the master (host) asserts the SCS (serial chip select) pin low (see Figure 32). The first rising edge of the clock signal (SCL) transfers the bit presented on the SDI pin of the CDCUN1208LP. This bit signals if a read (first bit high) or a write (first bit low) will transpire. The master shifts data to the slave with each rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the target register in the register file (see Figure 33). The 16 bits that follow are the data payload. If the master sends an incomplete message, (that is, the master de-asserts the SCS pin high prior to a complete message transmission), then the slave aborts the transfer, and device makes no changes to the register file or the hardware. The master signals the slave of the completed transfer and disables the SPI port by de-asserting the SCS pin high. At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in single-slave SPI configuration.