SLPS598C May   2017  – January 2018 CSD88584Q5DC


  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Brushless DC Motor With Trapezoidal Control
    3. 6.3 Power Loss Curves
    4. 6.4 Safe Operating Area (SOA) Curve
    5. 6.5 Normalized Power Loss Curves
    6. 6.6 Design Example – Regulate Current to Maintain Safe Operation
    7. 6.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
      1. 6.7.1 Operating Conditions
      2. 6.7.2 Calculating Power Loss
      3. 6.7.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Considerations
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5DC Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DMM|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Performance

The CSD88584Q5DC power block has the ability to switch at voltage rates greater than 1 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors; high-current, high dI/dT switching path; current shunt resistors; and GND return planes. As with any high-power inverter operated in hard switching mode, there will be voltage ringing present on the switch nodes U, V, and W. Switch-node ringing appears mainly at the HS FET turnon commutation with positive winding current direction. The U, V, and W phase connections to the BLDC motor can be usually excluded from the ringing behavior since they are subjected to high-peak currents but low dI/dT slew-rates. However, a compact PCB design with short and low-parasitic loop inductances is critical to achieve low ringing and compliance with EMI specifications.

For safe and reliable operation of the three-phase inverter, motor phase currents have to be accurately monitored and reported to the system microcontroller. One current sensor needs to be connected on each motor phase winding U, V, and W. This sensing method is best for current sensing as it provides good accuracy over a wide range of duty cycles, motor torque, and winding currents. Using current sensors is recommended because it is less intrusive to the VIN and GND connections.

CSD88584Q5DC Ring_Reduction.gifFigure 22. Recommended Ringing Reduction Components

However, for cost sensitive applications, current sensors are generally replaced with current sense resistors.

  • For designs using the 60-V three-phase smart gate driver DRV8320SRHBR, only one current sense resistor RCS can be placed between common source terminals for all 3 power block devices CSD88584Q5DC to PGND as depicted in Figure 22 above.
  • For designs using the 60-V three-phase gate driver DRV8323RSRGZT, three current sense resistors RCS1, RCS2, and RCS3 are being used between each CSD88584Q5DC source terminal to GND. The three-phase driver IC should be placed as close as possible to the power block gate GL and GH terminals.

Breaking the high-current flow path from the source terminals of the power block to GND by introducing the RCS current shunt resistors introduces parasitic PCB inductance. In the event the switch node waveforms exhibits peak ringing that reaches undesirable levels, the ringing can be reduced by using the following ringing reduction components:

  • The use of a high-side gate resistor in series with the GH pin is one effective way to reduce peak ringing. The recommended HS FET gate resistor value will range between 4.7 Ω to 10 Ω depending on the driver IC output characteristics used in conjunction with the power block device. The low-side FET gate pin GL should connect directly to the driver IC output to avoid any parasitic cdV/dT turnon effect.
  • Low inductance MLCC caps C4, C5, and C6 can be used across each power block device from VIN to the source terminal PGND. MLCC 10 nF, 100 V, ±10%, X7S, 0402, PN: C1005X7S2A103K050BB are recommended.
  • Ringing can be reduced via the implementation of RC snubbers from each switch node U, V, and W to GND. Recommended snubber component values are as follows:
    • Snubber resistors Rs1, Rs2, Rs3: 2.21 Ω, 1%, 0.125 W, 0805, PN: CRCW08052R21FKEA
    • Snubber caps Cs1, Cs2, and Cs3: MLCC 4.7 nF, 100 V, X7S, 0402, PN: C1005X7S2A472M050BB

With a switching frequency of 20 kHz on the three-phase inverter, the power dissipation on the RC snubber resistor is 80 mW per channel. As a result, 0805 package size for resistors Rs1, Rs2, and Rs3 is adequate.