SNAS321G June   2005  – April 2016 DAC101S101 , DAC101S101-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings DAC101S101
    3. 7.3 ESD Ratings DAC101S101-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 A.C. and Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
      3. 8.5.3 DSP/Microprocessor Interfacing
        1. 8.5.3.1 ADSP-2101/ADSP2103 Interfacing
        2. 8.5.3.2 80C51/80L51 Interface
        3. 8.5.3.3 68HC11 Interface
        4. 8.5.3.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4130
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • DAC101S101Q is AEC-Q100 Grade 1 Qualified and is Manufactured on an Automotive Grade Flow.
  • Ensured Monotonicity
  • Low Power Operation
  • Rail-to-Rail Voltage Output
  • Power-on Reset to Zero Volts Output
  • Wide Temperature Range of −40°C to +125°C
  • Wide Power Supply Range of 2.7 V to 5.5 V
  • Small Packages
  • Power Down Feature
  • Resolution 10 bits
  • DNL +0.15, –0.05 LSB (typical)
  • Output Settling Time 8 μs (typical)
  • Zero Code Error 3.3 mV (typical)
  • Full-Scale Error −0.06 %FS (typical)
  • Power Consumption
    • Normal Mode, 0.63 mW (3.6 V) / 1.41 mW (5.5 V) typical
    • Power Down Mode, 0.14 μW (3.6 V) / 0.33 μW (5.5 V) typical

2 Applications

  • Battery-Powered Instruments
  • Digital Gain and Offset Adjustment
  • Programmable Voltage & Current Sources
  • Programmable Attenuators
  • Automotive

3 Description

The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7 V to 5.5 V supply and consumes just 175 µA of current at 3.6 Volts. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces. Competitive devices are limited to 20 MHz clock rates at supply voltages in the 2.7 V to 3.6 V range.

The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC101S101 VSSOP (8) 3.00 mm × 3.00 mm
DAC101S101,
DAC101S101-Q1		 SOT-23 (6) 1.60 mm × 2.90 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

DNL at VA = 3 V

DAC101S101 DAC101S101-Q1 20154152.png