SNAS321G June   2005  – April 2016 DAC101S101 , DAC101S101-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings DAC101S101
    3. 7.3 ESD Ratings DAC101S101-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 A.C. and Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
      3. 8.5.3 DSP/Microprocessor Interfacing
        1. 8.5.3.1 ADSP-2101/ADSP2103 Interfacing
        2. 8.5.3.2 80C51/80L51 Interface
        3. 8.5.3.3 68HC11 Interface
        4. 8.5.3.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4130
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3)
MIN MAX UNIT
Supply voltage, VA 6.5 V
Voltage on any input pin –0.3 (VA + 0.3) V
Input current at any pin (4) 10 mA
Package input current (4) 20 mA
Power consumption at TA = 25°C See (5)
Storage temperature, Tstg −65 150 °C

7.2 ESD Ratings DAC101S101

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2500 V
Machine Model ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

7.3 ESD Ratings DAC101S101-Q1

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2500 V
Machine Model ±250
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.4 Recommended Operating Conditions(1) (3)

MIN MAX UNIT
Operating temperature DAC101S101 −40°C ≤ TA ≤ +105°C
DAC101S101-Q1 −40°C ≤ TA ≤ +125°C
Supply voltage, VA(7) 2.7 5.5 V
Any input voltage (6) –0.1 (VA + 0.1) V
Output load 0 1500 pF
SCLK frequency Up to 30 MHz

7.5 Thermal Information

THERMAL METRIC(1) DAC101S101,
DAC101S101-Q1		 DAC101S101 UNIT
DDC (SOT-23) DGK (VSSOP)
6 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 250 240 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.8 70.0 °C/W
RθJB Junction-to-board thermal resistance 30.6 100.2 °C/W
ψJT Junction-to-top characterization parameter 1.6 11.3 °C/W
ψJB Junction-to-board characterization parameter 30.1 98.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics

The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011, TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(8) TYP (8) MAX (8) UNIT
STATIC PERFORMANCE
Resolution DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 10 Bits
Monotonicity DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 10 Bits
INL Integral non-linearity Over decimal codes 12 to 1011 ±0.6 LSB
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C –2.8 2.8
DNL Differential
non-linearity		 VA = 2.7 V to 5.5 V −0.05/+0.15 LSB
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C −0.2 0.35
ZE Zero code error IOUT = 0 3.3 mV
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 15
FSE Full-scale error IOUT = 0 −0.06 %FSR
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C –1
GE Gain error All ones Loaded to DAC register −0.1 %FSR
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C –1 1
ZCED Zero code error drift −20 µV/°C
TC GE Gain error tempco VA = 3 V −0.7 ppm/°C
VA = 5 V −1 ppm/°C
OUTPUT CHARACTERISTICS
Output voltage range DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C (9) 0 VA V
ZCO Zero code output VA = 3 V, IOUT = 10 µA 1.8 mV
VA = 3 V, IOUT = 100 µA 5 mV
VA = 5 V, IOUT = 10 µA 3.7 mV
VA = 5 V, IOUT = 100 µA 5.4 mV
FSO Full scale output VA = 3 V, IOUT = 10 µA 2.997 V
VA = 3 V, IOUT = 100 µA 2.99 V
VA = 5 V, IOUT = 10 µA 4.995 V
VA = 5 V, IOUT = 100 µA 4.992 V
Maximum load capacitance RL = ∞ 1500 pF
RL = 2 kΩ 1500 pF
DC output Impedance 1.3 Ω
IOS Output short circuit current VA = 5 V, VOUT = 0 V,
Input code = 3FFh		 −63 mA
VA = 3 V, VOUT = 0 V,
Input code = 3FFh		 −50 mA
VA = 5 V, VOUT = 5 V,
Input code = 000h		 74 mA
VA = 3 V, VOUT = 3 V,
Input code = 000h		 53 mA
LOGIC INPUT
IIN Input current (9) DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C –1 1 µA
VIL Input low voltage (9) VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 0.8 V
VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 0.5 V
VIH Input high voltage (9) VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 2.4 V
VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 2.1 V
CIN Input capacitance (9) DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 3 pF
POWER REQUIREMENTS
IA Supply current
(output unloaded)		 Normal Mode
fSCLK = 30 MHz		 VA = 5.5 V 256 µA
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 332
VA = 3.6 V 174 µA
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 226
Normal Mode
fSCLK = 20 MHz		 VA = 5.5 V 221 µA
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 297
VA = 3.6 V 154 µA
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 207
Normal Mode
fSCLK = 0		 VA = 5.5 V 145 µA
VA = 3.6 V 113
All PD Modes,
fSCLK = 30 MHz		 VA = 5 V 83 µA
VA = 3 V 42
All PD Modes,
fSCLK = 20 MHz		 VA = 5 V 56 µA
VA = 3 V 28
All PD Modes,
fSCLK = 0 (9)		 VA = 5.5 V 0.06 µA
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 1
VA = 3.6 V 0.04 µA
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 1
PC Power consumption (output unloaded) Normal Mode
fSCLK = 30 MHz		 VA = 5.5 V 1.41 mW
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 1.83
VA = 3.6 V 0.63 mW
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 0.81
Normal Mode
fSCLK = 20 MHz		 VA = 5.5 V 1.22 mW
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 1.63
VA = 3.6 V 0.55 mW
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 0.74
Normal Mode
fSCLK = 0		 VA = 5.5 V 0.8 µW
VA = 3.6 V 0.41 µW
All PD Modes,
fSCLK = 30 MHz		 VA = 5 V 0.42 µW
VA = 3 V 0.13 µW
All PD Modes,
fSCLK = 20 MHz		 VA = 5 V 0.28 µW
VA = 3 V 0.08 µW
All PD Modes,
fSCLK = 0 (9)		 VA = 5.5 V 0.33 µW
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 5.5
VA = 3.6 V 0.14 µW
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 3.6
IOUT / IA Power efficiency ILOAD = 2 mA VA = 5 V 91%
VA = 3 V 94%

7.7 A.C. and Timing Requirements

The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011, TA = 25°C, unless otherwise specified.
MIN(8) TYP(8) MAX(8) UNIT
fSCLK SCLK Frequency DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 30 MHz
ts Output voltage settling time (9) 100h to 300h code change, RL = 2 kΩ CL ≤ 200 pF 5 µs
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 7.5
SR Output slew rate 1 V/µs
Glitch impulse Code change from 200h to 1FFh 12 nV-sec
Digital feedthrough 0.5 nV-sec
tWU Wake-up time VA = 5 V 6 µs
VA = 3 V 39 µs
1/fSCLK SCLK Cycle time DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 33 ns
tH SCLK High time 5 ns
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 13
tL SCLK Low time 5 ns
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 13
tSUCL Set-up time SYNC to SCLK rising edge −15 ns
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 0
tSUD Data set-up time 2.5 ns
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 5
tDHD Data hold time 2.5 ns
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C		 4.5
tCS SCLK fall to rise of SYNC VA = 5 V 0 ns
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 3
VA = 3 V −2 ns
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 1
tSYNC SYNC High time 2.7 ≤ VA ≤ 3.6 9 ns
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 20
3.6 ≤ VA ≤ 5.5 5 ns
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 10
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) All voltages are measured with respect to GND = 0V, unless otherwise specified
(4) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
(6) The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions.
DAC101S101 DAC101S101-Q1 20154104.gif
(7) To ensure accuracy, it is required that VA be well bypassed.
(8) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(9) This parameter is ensured by design and/or characterization and is not tested in production.
DAC101S101 DAC101S101-Q1 20154105.gif Figure 1. Input / Output Transfer Characteristic
DAC101S101 DAC101S101-Q1 20154106.gif Figure 2. Serial Timing Diagram

7.8 Typical Characteristics

fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
DAC101S101 DAC101S101-Q1 20154152.png Figure 3. DNL at VA = 3 V
DAC101S101 DAC101S101-Q1 20154154.png Figure 5. INL at VA = 3 V
DAC101S101 DAC101S101-Q1 20154156.png Figure 7. TUE at VA = 3 V
DAC101S101 DAC101S101-Q1 20154122.png Figure 9. DNL vs. VA
DAC101S101 DAC101S101-Q1 20154150.png Figure 11. 3-V DNL vs. fSCLK
DAC101S101 DAC101S101-Q1 20154124.png Figure 13. 3-V DNL vs. Clock Duty Cycle
DAC101S101 DAC101S101-Q1 20154126.png Figure 15. 3-V DNL vs. Temperature
DAC101S101 DAC101S101-Q1 20154128.png Figure 17. 3-V INL vs. fSCLK
DAC101S101 DAC101S101-Q1 20154130.png Figure 19. 3-V INL vs. Clock Duty Cycle
DAC101S101 DAC101S101-Q1 20154132.png Figure 21. 3-V INL vs. Temperature
DAC101S101 DAC101S101-Q1 20154134.png Figure 23. Zero Code Error vs. fSCLK
DAC101S101 DAC101S101-Q1 20154136.png Figure 25. Zero Code Error vs. Temperature
DAC101S101 DAC101S101-Q1 20154138.png Figure 27. Full-Scale Error vs. Clock Duty Cycle
DAC101S101 DAC101S101-Q1 20154144.png Figure 29. Supply Current vs. VA
DAC101S101 DAC101S101-Q1 20154146.png Figure 31. 5-V Glitch Response
DAC101S101 DAC101S101-Q1 20154148.png Figure 33. 3-V Wake-Up Time
DAC101S101 DAC101S101-Q1 20154153.png Figure 4. DNL at VA = 5 V
DAC101S101 DAC101S101-Q1 20154155.png Figure 6. INL at VA = 5 V
DAC101S101 DAC101S101-Q1 20154157.png Figure 8. TUE at VA = 5 V
DAC101S101 DAC101S101-Q1 20154123.png Figure 10. INL vs. VA
DAC101S101 DAC101S101-Q1 20154151.png Figure 12. 5-V DNL vs. fSCLK
DAC101S101 DAC101S101-Q1 20154125.png Figure 14. 5-V DNL vs. Clock Duty Cycle
DAC101S101 DAC101S101-Q1 20154127.png Figure 16. 5-V DNL vs. Temperature
DAC101S101 DAC101S101-Q1 20154129.png Figure 18. 5-V INL vs. fSCLK
DAC101S101 DAC101S101-Q1 20154131.png Figure 20. 5-V INL vs. Clock Duty Cycle
DAC101S101 DAC101S101-Q1 20154133.png Figure 22. 5-V INL vs. Temperature
DAC101S101 DAC101S101-Q1 20154135.png Figure 24. Zero Code Error vs. Clock Duty Cycle
DAC101S101 DAC101S101-Q1 20154137.png Figure 26. Full-Scale Error vs. fSCLK
DAC101S101 DAC101S101-Q1 20154139.png Figure 28. Full-Scale Error vs. Temperature
DAC101S101 DAC101S101-Q1 20154145.png Figure 30. Supply Current vs. Temperature
DAC101S101 DAC101S101-Q1 20154147.png Figure 32. Power-On Reset
DAC101S101 DAC101S101-Q1 20154149.png Figure 34. 5-V Wake-Up Time