SNAS362G May   2006  – April 2016 DAC104S085 , DAC104S085-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings - DAC104S085
    3. 7.3 ESD Ratings - DAC104S085-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Amplifiers
      2. 8.3.2 Reference Voltage
      3. 8.3.3 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
      2. 8.4.2 Bipolar Operation
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
      3. 8.5.3 DSP and Microprocessor Interfacing
        1. 8.5.3.1 ADSP-2101 and ADSP2103 Interfacing
        2. 8.5.3.2 80C51 and 80L51 Interface
        3. 8.5.3.3 68HC11 Interface
        4. 8.5.3.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 LM4130
      2. 9.1.2 LP3985
      3. 9.1.3 LP2980
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Specification Definitions
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings (1)(2)(3)

MIN MAX UNIT
Supply voltage, VA 6.5 V
Voltage on any input pin −0.3 6.5 V
Input current at any pin(4) 10 mA
Package input current(4) 20 mA
Power consumption at TA = 25°C See (5)
Junction temperature 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

7.2 ESD Ratings – DAC104S085

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2500 V
Machine model (MM) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.

7.3 ESD Ratings – DAC104S085-Q1

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2500 V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.4 Recommended Operating Conditions(1)

MIN MAX UNIT
Operating temperature –40 125 °C
Supply voltage, VA 2.7 5.5 V
Reference voltage, VREFIN 1 VA V
Digital input voltage(2) 0 5.5 V
Output load 0 1500 pF
SCLK frequency 40 MHz
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected as shown. Input voltage magnitudes up to 5.5 V, regardless of VA, does not cause errors in the conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.
DAC104S085 DAC104S085-Q1 20195304.gif

7.5 Thermal Information

THERMAL METRIC(1)(2)(3) DAC104S085-xx UNIT
DGS (VSSOP) DSC (SON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 159 48.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.3 40.7 °C/W
RθJB Junction-to-board thermal resistance 78.9 23.7 °C/W
ψJT Junction-to-top characterization parameter 4.8 0.4 °C/W
ψJB Junction-to-board characterization parameter 77.6 23.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Soldering process must comply with Reflow Temperature Profile specifications. See the Absolute Maximum Ratings for Soldering application report, SNOA549, for more information.
(3) Reflow temperature profiles are different for lead-free packages.

7.6 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(1) MAX(1) UNIT
STATIC PERFORMANCE
Resolution TMIN ≤ TA ≤ TMAX 10 Bits
Monotonicity TMIN ≤ TA ≤ TMAX 10 Bits
INL Integral non-linearity ±0.7 LSB
TMIN ≤ TA ≤ TMAX ±2
DNL Differential non-linearity VA = 2.7 V to 5.5 V −0.03 0.08 LSB
TMIN ≤ TA ≤ TMAX −0.25 0.35
ZE Zero code error IOUT = 0 mA 5 mV
TMIN ≤ TA ≤ TMAX 15
FSE Full-scale error IOUT = 0 mA −0.1 %FSR
TMIN ≤ TA ≤ TMAX −0.75
GE Gain error All ones Loaded to DAC register −0.2 %FSR
TMIN ≤ TA ≤ TMAX −1
ZCED Zero code error drift −20 µV/°C
TC GE Gain error tempco VA = 3 V −0.7 ppm/°C
VA = 5 V −1
OUTPUT CHARACTERISTICS
Output voltage range See(2), TMIN ≤ TA ≤ TMAX 0
VREFIN 		0
VREFIN 		V
IOZ High-impedance output
leakage current(2)		 TMIN ≤ TA ≤ TMAX ±1 µA
ZCO Zero code output VA = 3 V, IOUT = 200 µA 1.3 mV
VA = 3 V, IOUT = 1 mA 6
VA = 5 V, IOUT = 200 µA 7
VA = 5 V, IOUT = 1 mA 10
FSO Full-scale output VA = 3 V, IOUT = 200 µA 2.984 V
VA = 3 V, IOUT = 1 mA 2.934
VA = 5 V, IOUT = 200 µA 4.989
VA = 5 V, IOUT = 1 mA 4.958
IOS Output short-circuit current (source) VA = 3 V, VOUT = 0 V,
Input Code = 3FFh		 –56 mA
VA = 5 V, VOUT = 0 V,
Input Code = 3FFh		 –69
IOS Output short-circuit current (sink) VA = 3 V, VOUT = 3 V,
Input Code = 000h		 52 mA
VA = 5 V, VOUT = 5 V,
Input Code = 000h		 75
IO Continuous output
current(2)		 Available on each DAC output, TMIN ≤ TA ≤ TMAX 11 mA
CL Maximum load capacitance RL = ∞ 1500 pF
RL = 2 kΩ 1500
ZOUT DC output impedance 7.5 Ω
REFERENCE INPUT CHARACTERISTICS
VREFIN Input range minimum 0.2 V
TMIN ≤ TA ≤ TMAX 1
Input range maximum TMIN ≤ TA ≤ TMAX VA V
Input impedance 30 kΩ
LOGIC INPUT CHARACTERISTICS
IIN Input current(2) TMIN ≤ TA ≤ TMAX ±1 µA
VIL Input low voltage(2) VA = 3 V 0.9 V
TMIN ≤ TA ≤ TMAX 0.6
VA = 5 V 1.5 V
TMIN ≤ TA ≤ TMAX 0.8
VIH Input high voltage(2) VA = 3 V 1.4 V
TMIN ≤ TA ≤ TMAX 2.1
VA = 5 V 2.1 V
TMIN ≤ TA ≤ TMAX 2.4
CIN Input capacitance(2) TMIN ≤ TA ≤ TMAX 3 pF
POWER REQUIREMENTS
VA(3) Supply voltage minimum TMIN ≤ TA ≤ TMAX 2.7 V
Supply voltage maximum TMIN ≤ TA ≤ TMAX 5.5 V
IN Normal supply current (output unloaded) fSCLK = 30 MHz VA = 2.7 V
to 3.6 V		 350 µA
TMIN ≤ TA ≤ TMAX 485
VA = 4.5 V
to 5.5 V		 500 µA
TMIN ≤ TA ≤ TMAX 650
fSCLK = 0 MHz VA = 2.7 V
to 3.6 V		 330 µA
VA = 4.5 V
to 5.5 V		 460 µA
IPD Power-down supply current (output unloaded, SYNC = DIN = 0V after PD mode loaded) All PD Modes,(2) VA = 2.7 V
to 3.6 V		 0.1 µA
TMIN ≤ TA ≤ TMAX 1
VA = 4.5 V
to 5.5 V		 0.15 µA
TMIN ≤ TA ≤ TMAX 1
PN Normal supply power (output unloaded) fSCLK = 30 MHz VA = 2.7 V
to 3.6 V		 1.1 mW
TMIN ≤ TA ≤ TMAX 1.7
VA = 4.5 V
to 5.5 V		 2.5 mW
TMIN ≤ TA ≤ TMAX 3.6
fSCLK = 0 MHz VA = 2.7 V
to 3.6 V		 1 mW
VA = 4.5 V
to 5.5 V		 2.3 mW
PPD Power-down supply power (output unloaded, SYNC = DIN = 0V after PD mode loaded) All PD Modes,(2) VA = 2.7 V
to 3.6 V		 0.3 µW
TMIN ≤ TA ≤ TMAX 3.6
VA = 4.5 V
to 5.5 V		 0.8 µW
TMIN ≤ TA ≤ TMAX 5.5
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
(3) To ensure accuracy, it is required that VA and VREFIN be well bypassed.

7.7 Timing Requirements

Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
MIN(1) TYP(1) MAX(1) UNIT
fSCLK SCLK frequency 40 MHz
TMIN ≤ TA ≤ TMAX 30
ts Output voltage settling time(2) 100h to 300h code change
RL = 2 kΩ, CL = 200 pF		 4.5 µs
TMIN ≤ TA ≤ TMAX 6
SR Output slew rate 1 V/µs
Glitch impulse Code change from 200h to 1FFh 12 nV-sec
Digital feedthrough 0.5 nV-sec
Digital crosstalk 1 nV-sec
DAC-to-DAC crosstalk 3 nV-sec
Multiplying bandwidth VREFIN = 2.5 V ± 0.1 Vpp 160 kHz
Total harmonic distortion VREFIN = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz		 70 dB
tWU Wake-up time VA = 3 V 6 µsec
VA = 5 V 39 µsec
1/fSCLK SCLK cycle time 25 ns
TMIN ≤ TA ≤ TMAX 33
tCH SCLK high time 7 ns
TMIN ≤ TA ≤ TMAX 10
tCL SCLK low Time 7 ns
TMIN ≤ TA ≤ TMAX 10
tSS SYNC set-up time prior to SCLK falling edge 4 ns
TMIN ≤ TA ≤ TMAX 10
tDS Data set-up time prior to SCLK falling edge 1.5 ns
TMIN ≤ TA ≤ TMAX 3.5
tDH Data hold time after SCLK falling edge 1.5 ns
TMIN ≤ TA ≤ TMAX 3.5
tCFSR SCLK fall prior to rise of SYNC 0 ns
TMIN ≤ TA ≤ TMAX 3
tSYNC SYNC high time 6 ns
TMIN ≤ TA ≤ TMAX 10
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
DAC104S085 DAC104S085-Q1 20195306.gif Figure 1. Serial Timing Diagram
DAC104S085 DAC104S085-Q1 20195305.gif Input / Output Transfer Characteristic

7.8 Typical Characteristics

VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range from 12 to 1011, unless otherwise stated
DAC104S085 DAC104S085-Q1 20195352.png Figure 2. INL at VA = 3 V
DAC104S085 DAC104S085-Q1 20195354.png Figure 4. DNL at VA = 3 V
DAC104S085 DAC104S085-Q1 20195356.png Figure 6. INL/DNL vs VREFIN at VA = 3 V
DAC104S085 DAC104S085-Q1 20195350.png Figure 8. INL/DNL vs fSCLK at VA = 2.7 V
DAC104S085 DAC104S085-Q1 20195324.png Figure 10. INL/DNL vs Clock Duty Cycle at VA = 3 V
DAC104S085 DAC104S085-Q1 20195326.png Figure 12. INL/DNL vs Temperature at VA = 3 V
DAC104S085 DAC104S085-Q1 20195330.png Figure 14. Zero Code Error vs VA
DAC104S085 DAC104S085-Q1 20195334.png Figure 16. Zero Code Error vs fSCLK
DAC104S085 DAC104S085-Q1 20195336.png Figure 18. Zero Code Error vs Temperature
DAC104S085 DAC104S085-Q1 20195332.png Figure 20. Full-Scale Error vs VREFIN
DAC104S085 DAC104S085-Q1 20195338.png Figure 22. Full-Scale Error vs Clock Duty Cycle
DAC104S085 DAC104S085-Q1 20195344.png Figure 24. Supply Current vs VA
DAC104S085 DAC104S085-Q1 20195353.png Figure 3. INL at VA = 5 V
DAC104S085 DAC104S085-Q1 20195355.png Figure 5. DNL at VA = 5 V
DAC104S085 DAC104S085-Q1 20195357.png Figure 7. INL/DNL vs VREFIN at VA = 5 V
DAC104S085 DAC104S085-Q1 20195322.png Figure 9. INL/DNL vs VA
DAC104S085 DAC104S085-Q1 20195325.png Figure 11. INL/DNL vs Clock Duty Cycle at VA = 5 V
DAC104S085 DAC104S085-Q1 20195327.png Figure 13. INL/DNL vs Temperature at VA = 5 V
DAC104S085 DAC104S085-Q1 20195331.png Figure 15. Zero Code Error vs. VREFIN
DAC104S085 DAC104S085-Q1 20195335.png Figure 17. Zero Code Error vs Clock Duty Cycle
DAC104S085 DAC104S085-Q1 20195337.png Figure 19. Full-Scale Error vs VA
DAC104S085 DAC104S085-Q1 20195333.png Figure 21. Full-Scale Error vs fSCLK
DAC104S085 DAC104S085-Q1 20195339.png Figure 23. Full-Scale Error vs Temperature
DAC104S085 DAC104S085-Q1 20195345.png Figure 25. Supply Current vs Temperature