The DACx1001 R2R ladder and deglitch circuit reduce the harmonic distortion for waveform generation applications. The fast settling bit (FSET, bit 10, address 02h) is set to 1 by default, so that the DAC is configured for enhanced THD performance. The FSET bit can be reset to 0 using an SPI write to enable fast-settling mode. In this mode, the DAC deglitcher circuit can be configured using TNH_MASK (bits 19:18, address 02h). These bits disable the deglitch circuit for code changes specified in Table 11. These bits are only writable when FSET = 0 (fast settling enabled) and DIS_TNH = 0 (deglitch circuit enabled).