SBAS649B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
The FIFO_DLY_R0 through FIFO_DLY_R3 values provide an approximate value for FIFO_DLY that would result in the sample being used just as it arrives for each channel. These values are asynchronously sampled between clock domains and may vary from channel to channel even with exactly the same relationship between DCLK and DACCLK.
If all four LVDS clocks have the same relationship to the consuming DACCLK (i.e., LVDS clocks DACLK - DDCLK are staggered as shown in LVDS Input waveforms), all FIFO_DLY_R* values should vary by no more than 1 (in a circular sense). If the LVDS clocks are aligned in time, this will result in successive FIFO_DLY_R* values increasing by 1±1. The user must select a FIFO_DLY setting that will work for all banks.
The valid programming range for FIFO_DLY and FIFO_DLY_R* is shown in the following table.