SBAS649B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Timing Requirements

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, single channel (MODE2) at 6.4 GSPS, single tone amplitude = 0 dBFS, unless otherwise noted.
MIN NOM MAX UNIT
INPUT CLOCK (CLKIN+, CLKIN-)
fCLK Input clock frequency 800 6400 MHz
LVDS INTERFACE
fBIT Dx[11:0]+/- DDR data rate 1600 Mbps
UI Dx[11:0]+/- DDR data unit interval 625 ps
tSU(LVDS) Setup time, Dx[11:0]+/– and DxSTR+/– valid to DxCLK+/– rising or falling edge All LVDS buses -375 -240 ps
tH(LVDS) Hold time, DxCLK+/– rising or falling edge to Dx[11:0]+/– and DxSTR+/– transition All LVDS buses 495 565 ps
fDCLK DxCLK+/- DDR data clock frequency 800 MHz
TRIGGER CLOCK
FTRIGCLKMAX Trigger clock maximum frequency 100 MHz
tS_TRIGCLK setup time for NCO_SEL[3:0] and NCOBANKSEL to TRIGCLK rising edge 3.5 ns
tH_TRIGCLK hold  time for NCO_SEL[3:0] and NCOBANKSEL to TRIGCLK rising edge -1.5 ns
SYSREF (SYSREF+, SYSREF-)
tINV(SYSREF) Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register(1) 48 ps
tINV(TEMP) Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register -0.12 ps/°C
tINV(VDDHAF) Drift of invalid SYSREF capture region over VDDHAF supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register 0.33 ps/mV
tSTEP(SP) Delay of SYSREF_SEL LSB SYSREF_ZOOM = 0 22 ps
SYSREF_ZOOM = 1 9
t(PH_SYS) Minimum SYSREF± assertion duration after SYSREF± rising edge event 4 ns
RESET
tRESET Minimum RESET pulse width 25 ns
(1) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the section Multi-Device Synchronization (SYSREF+/-) for more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period(tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.