SLAS959D August 2013 – February 2018 DAC3151 , DAC3161 , DAC3171
PRODUCTION DATA.
Register Name | Addr (Hex) | Bit | Name | Function | Default Value |
---|---|---|---|---|---|
config5 WRITE TO CLEAR | 0x05 | 15 | alarm_from_ zerochka | When this bit is asserted the FIFOA write pointer has an all zeros pattern in it. Since this pointer is a shift register, all zeros will cause the input point to be stuck until the next sync. The result could be a repeated 8T pattern at the output if the mixer is off and no syncs occur. Check for this error will tell the user that another sync is necessary to restart the FIFO write pointer. | 0 |
14 | reserved | reserved. | 0 | ||
13:11 | alarms_from_ fifoa | These bits report the FIFO A pointer status. 000: All fine 001: Pointers are 2 away 01X: Pointers are 1 away 1XX: FIFO Pointer collision |
000 | ||
10:8 | reserved | reserved | 0 | ||
7 | alarm_dacclk_ gone | Bit gets asserted when the DACCLK has been stopped long for enough cycles to be caught. The number of cycles varies with interpolation. | 0 | ||
6 | alarm_dataclk_ gone | Bit gets asserted when the DATACLK has been stopped long for enough cycles to be caught. The number of cycles varies with interpolation. | 0 | ||
5 | clock_gone | This bit gets set when either alarm_dacclk_gone or alarm_dataclk_gone are asserted. It controls the output of the CDRV_SER block. When high, the CDRV_SER block will output 0x8000 for each output connected to a DAC. The bit must be written to ‘0’ for CDRV_SER outputs to resume normal operation. | 0 | ||
4 | alarm_from_ iotesta | This is asserted when the input data pattern does not match the pattern in the iotest_pattern registers. | 0 | ||
3 | reserved | reserved. | 0 | ||
2 | reserved | reserved | 0 | ||
1 | reserved | reserved | 0 | ||
0 | reserved | reserved | 0 |